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EDMA3 : DMA-QDMA Conflict

Bharti Jain
Prodigy 240 points

Hi,

I was running a project in which I am trying to run QDMA & DMA together in EDMA3 ( TPCC2).

First I configure QDMA for channel number 64(the first QDMA Channel) & then I trigger the transfer on the same,

Next,I configure DMA for all the 64 channels one by one & trigger the corresponding transfer (using a for loop).

Following are my observations:

1. If I remove QDMA,all 64 DMA transfers are successful

2.With QDMA,if I initiate the DMA transfer in the order of  increasing channel number(0-63),the code gets stuck within the polling loop after 5-6 DMA transfers.

When I check corresponding IPR bit,I see that it does not get cleared after transfer completes but when QDMA was not there,there was no problem (observation 1)

3. With QDMA,now, if I reverse the order of DMA transfer(63-0),the code works fine & all the IPR bits keep getting cleared on corresponding completions.

Why is QDMA troubling here though according to  the document SPRUGS5A Section 2.1.2,DMA has higher priority than QDMA.

I was also wondering why the same QDMA did not create problem when I reversed the order of transfer.

If anyone has an idea,please let me know.

Device : TCI6618

Here is my code below:7343.edma_interrupt.rar

Regards,

Bharti

  • 0
    TI__Expert 5955 points

    Hi Bharti,

    Priority is not likely to be the culprit, since things will get interleaved at various points.

    I would suspect a resource allocation issue? Please check that unique PaRAM entries and unique TCC code are being used for all.

    Thanks and regards,

    Tai

  • 0 in reply to Tai Nguyen
    Prodigy 240 points

    Tai,

    If it was resource allocation issue,then why would the code work well on reversing the order?

    & I am using unique PARAMs for all channels if you look into the code.

    -Bharti

  • 0 in reply to Bharti Jain
    TI__Expert 5955 points

    Bharti,

    From the code, it looks like you were using unique PaRAM for all the channels but can you verify it by viewing the PaRAM memory with the CCS memory windows to make sure there are no conflict between PaRAM for QDMA and DMA. 

    The reason that the code would work on reversing order could be that the time the PaRAM set was configured and used by one and the time it is configured and used again by the other was not overlapped.

    Thanks,

    -Tai

  • 0 in reply to Tai Nguyen
    TI__Guru* 84110 points

    Bharti,

    Tai gave you the most likely problem and analysis in his first post: resource conflict and TCC codes.

    Your test code is an example of trying to test something that you do not need to test, since this is not a practical application. There is no situation where you would be trying to manually trigger all 64 DMA channels AND a QDMA channel and try to get them to work in some artificial order.

    There are only 64 IPR/IPRH bits and only 64 TCC codes, so it is impossible to use 64 DMA channels plus 1 QDMA channel and have them all have unique TCC codes. When you run one direction through the list, your QDMA interferes or overlaps with one of the DMA channels at a time that causes the code to fail. When you run through the list in the other direction, your code is not sensitive to this or fails to catch the error.

    I have not looked at the code, so I cannot tell you where your code logic error is. But it is clear where your test system error is by the number of TCC codes required.

    Try removing the one DMA channel that uses the same TCC code as the QDMA channel, then see if your program runs better.

    Regards,
    RandyP