DM8148 uboot: nand speed is very low?

hi Jiangao,

Could you please provide more details? What command for nand read you are using? I just try this on my own DM8148 EVM:

TI8148_EVM# nand read 0x80000000 0x400000 0x400000

And it works for less than a second:

NAND read: device 0 offset 0x400000, size 0x40000
 262144 bytes read: OK

Best regards,

Pavel

TI8148_EVM#nandecc hw 0
HW ECC Hamming Code selected
TI8148_EVM#nand read 81000000 400000 400000

NAND read: device 0 offset 0x400000, size 0x400000
 4194304 bytes read: OK
TI8148_EVM#

it takes about 7 seconds, it's too slow.

My uboot: u-boot-2010.06-psp04.01.00.06

hi Jiangao,

When I try TI8148_EVM#nand read 81000000 400000 400000, it takes about 3 seconds. And I am with the newest u-boot: u-boot-2010.06-psp04.04.00.01. This u-boot is available in the new DM814x EZSDK 5.04.00.11. Could you please try with the new u-boot.

Best regards,

Pavel

I will have a try and let you know.

But, 1M/s is remain a low speed, there is any way to speed up it ?

thanks.

some information in my kernel:

gpmc_fck:      100000000

arm_dpll_ck: 600000000

mpu_ck:         600000000

GPMC_CONFIG1_0(d0804060) = 810
GPMC_CONFIG2_0(d0804064) = 1e1e00
GPMC_CONFIG3_0(d0804068) = 1e1e00
GPMC_CONFIG4_0(d080406c) = 16051807
GPMC_CONFIG5_0(d0804070) = 151e1e
GPMC_CONFIG6_0(d0804074) = 16000f80
GPMC_CONFIG7_0(d0804078) = 48

some info on my uboot:

U-Boot 2010.06 (Jun 09 2012 - 09:58:39)

TI8148-GP rev 2.1

ARM clk: 600MHz
DDR clk: 400MHz

DRAM:  2 GiB
NAND:  HW ECC BCH8 Selected

I test the nand speed use mtd_speedtest:

mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 1854 KiB/s
mtd_speedtest: testing eraseblock read speed

mtd_speedtest: eraseblock read speed is 2252 KiB/s
mtd_speedtest: testing page write speed

mtd_speedtest: page write speed is 1854 KiB/s
mtd_speedtest: testing page read speed

So, it looks like the nand speed in kernel is not fast !

my question:

 1: 2M/s is a normal speed?

 2: How to speed up it ?

This is a mtd speed test of my another platform: (MLC, Hynix2GB)

[   40.070000]
[   40.070000] =================================================
[   40.072000] mtd_speedtest: MTD device: 4
[   40.076000] mtd_speedtest: MTD device size 16777216, eraseblock size 2097152, page size 8192, count of eraseblocks 8, pages per eraseblock 256, OOB size 448

[   40.345000] mtd_speedtest: scanning for bad eraseblocks
[   40.378000] mtd_speedtest: scanned 8 eraseblocks, 0 are bad
[   40.458000] mtd_speedtest: testing eraseblock write speed
[   44.870000] mtd_speedtest: eraseblock write speed is 3713 KiB/s
[   44.870000] mtd_speedtest: testing eraseblock read speed
[   46.220000] mtd_speedtest: eraseblock read speed is 12190 KiB/s
[   46.275000] mtd_speedtest: testing page write speed

[   54.200000] mtd_speedtest: page write speed is 2067 KiB/s
[   54.200000] mtd_speedtest: testing page read speed
[   55.374000] mtd_speedtest: page read speed is 14003 KiB/s
[   55.395000] mtd_speedtest: testing 2 page write speed

[   59.346000] mtd_speedtest: 2 page write speed is 4146 KiB/s
[   59.346000] mtd_speedtest: testing 2 page read speed
[   60.548000] mtd_speedtest: 2 page read speed is 13721 KiB/s
[   60.548000] mtd_speedtest: Testing erase speed
[   60.573000] mtd_speedtest: erase speed is 819200 KiB/s
[   60.573000] mtd_speedtest: finished
[   60.576000] =================================================
#

[   46.220000] mtd_speedtest: eraseblock read speed is 12190 KiB/s !

so , it is necessary to improve the dm8148 nand speed now.

Hi Jiangao,

We can try to speed up with increasing the CPU clock frequency (600 -> 1000 MHz) and GPMC clock frequency (100 -> 130 MHz).

1. To increase the CPU clock frequency, modify in file ${EZSDK}/board-support/u-boot-2010.06-psp04.04.00.01/arch/arm/include/asm/arch-ti81xx/clocks_ti814x.h, parameter MODENA_M to 0x64:

//#define MODENA_M    0x3C

#define MODENA_M    0x64

2. To increase the GPMC clock frequency, modify in file ${EZSDK}/board-support/u-boot-2010.06-psp04.04.00.01/arch/arm/include/asm/arch-ti81xx/clocks_ti814x.h, parameter L3_M to 1040:

//#define L3_M        (pg_val_ti814x(880, 800))

#define L3_M        (pg_val_ti814x(880, 1040))

Best regards,

Pavel

I have made some change in uboot:

#define MODENA_N 0x1
#define MODENA_M 0x64//0x3c//0x64
#define MODENA_M2 1
#define MODENA_CLKCTRL 0x1

#define L3_N  19
#define L3_M  (pg_val_ti814x(880, 1040/*800*/))
#define L3_M2  4
#define L3_CLKCTRL 0x801

#define DDR_N  19
#define DDR_M  (pg_val_ti814x(666, 800))
#define DDR_M2  2
#define DDR_CLKCTRL 0x801

#define DSP_N  19
#define DSP_M  750//500//750
#define DSP_M2  1
#define DSP_CLKCTRL 0x801

And this the uboot output:

U-Boot 2010.06 (Jun 12 2012 - 08:34:37)

TI8148-GP rev 2.1

ARM clk: 1000MHz
DDR clk: 400MHz

I2C:   ready
DRAM:  2 GiB
NAND:  HW ECC BCH8 Selected
nand dev_id = d3

Result:

i use "nand read 81000000 1000000 a00000" in uboot, and it takes almost 16 seconds !

TI8148_EVM#nand read 81000000 1000000 a00000

NAND read: device 0 offset 0x1000000, size 0xa00000
Skipping bad block 0x01360000
 10485760 bytes read: OK
TI8148_EVM#

So, is there another way to speed up it ?

Thank you very mush !

Ok, the speed is remain not In my expectations。

But thank you very much !

Jiangao & Pavel,

We've achieved around 8MB/sec throughput in DM8148EVM for NAND read. Please get in touch if you need a better solution. My mail id is renjith.thomas@pathpartnertech.com

Hi Renjith,

Could you please post here the following:

1. Your CPU clock frequency

2. Your GPMC fclk frequency

3. Is your NAND memory attached to CS0? If yes, please provide your GPMC_CONFIGx_0 (x = 1 to 7) registers settings

4. Is your NAND memory from Micron? If yes, what is the chip id?

Thanks,

Pavel

Pavel,

I made a mistake here, this was done on DM8168EVM and not on 8148. But GPMC is almost same. Please find the answers below.

1. ARM running @ 1GHz.

2. GPMC frequency we didn't change, whatever is set default by u-boot.

3. Its attached to CS0, as its EVM.

4. The NAND part on Netra EVM is Mircon MT29F2G16AADWP.

Hi Renjith,

Thanks for your answer.

One more thing, could you please give us your GPMC_CONFIGx_0 (x = 1 to 7) registers values?

For example, our values are:

GPMC_CONFIG1_0 = 1810
GPMC_CONFIG2_0 = 40400
GPMC_CONFIG3_0 = 40301
GPMC_CONFIG4_0 = 3010501
GPMC_CONFIG5_0 = 50707
GPMC_CONFIG6_0 = 16000f80
GPMC_CONFIG7_0 = f48

I want to verify that we are using the same.

Best regards,

Pavel

Pavel,

My timings are for Netra EVM and not for Centaurus. Still you can give it a shot

GPMC_CONFIG1 0x01001800
GPMC_CONFIG2 0x00000400
GPMC_CONFIG3 0x00160100
GPMC_CONFIG4 0x01000000
GPMC_CONFIG5 0x00031703
GPMC_CONFIG6 0x00000000
GPMC_CONFIG7 0x00000f48

Hi Renjith,

I tried with these, but there is no speed-up progress. May be these are valid only for Netra EVM.

When reading from NAND, are you using nandecc hw 0 (HW ECC Hamming Code)?

One last thing that I can try is to align my rest GPMC registers values with yours. So I need these registers values that you are using:GPMC_CONFIG, GPMC_STATUS, GPMC_PREFETCH_CONFIG1, GPMC_PREFETCH_CONFIG2, GPMC_PREFETCH_CONTROL, GPMC_ECC_CONFIG, GPMC_ECC_CONTROL, GPMC_ECC_SIZE_CONFIG, GPMC_BCH_SWDATA

Best regards,

Pavel

Pavel,

I dont think these changes are going to give you much gain. The problem lies not just in these register settings. You've to change the driver code to a certain extent. I'm afraid I'll not be able to disclose our optimization over the forum.

Hi pavel,

On what basis have you changed the register values of GPMC_CONFIG registers.

I see that according to the values suggested by you will change the number of GPMC_FCLK cycles.How are you calculating the GPMC_FCLK cycles?

For example: My current GPMC_FCLK2_0 value is 1e1e00 and the value suggested by you is 40400. When we decode this value, the De-assertion time from start cycle to read (bit[8] to bit[12]) is 4 GPMC_FCLK cycle. Can you please let me know how you are calculating the number of GPMC_FCLK cycles for different access?

Thanks in advance.

Regards

Prakash

Hi Prakash,

I changed the registers values of GPMC_CONFIG registers, based on the fact that in u-boot we have one set of settings, and in linux kernel we have other set of settings. I did not made any calculations for the GPMC_FCLK cycles. The reported issue was that in u-boot, the NAND read/write speed is slow, while in kernel, NAND speed is well. So what I did is to compare the settings in GPMC in kernel, and apply these into u-boot. Then the speed in u-boot get well also.

For how to calculate the GPMC_FCLK cycles, you can check here:

1. DM814x TRM, chapter 11 GPMC, section 11.2.4.9 Timing Setting, section 11.3.6 GPMC Timing Parameters, 11.4.1 How to Set GPMC Timing Parameters for Typical Accesses

2. http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x,_AM35x,_and_AM-DM37x_GPMC_registers

Regards,

Pavel

Hi pavel,

Thanks for your reply.

Could you let me know in which file in the kernel the GPMC_CONFIGi registers are present?

We are using 'micron NAND' and i am not able to find the GPMC_CONFIG registers to change their values suggested by you above.

Thanks

Prakash

Does anybody have any results with this problem?

We face to the same issue in u-boot. GPMC works with NAND flash very slow. We discovered that there is a long time between sequential read cycles during nand reading operation. The time when CS is inactive about 800ns. I couldn`t reduce this time. Any changing the CPMC_CONFIG settings do not affect.

It seems u-boot works quite slow in general, because we notice that ethernet works slower too in u-boot than in kernel.

Hi Evgeny,

Which version of the EZSDK you are using? Make sure you are using the latest one 5.05

You can check here also, for the expected performance:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.01_Feature_Performance_Guide#NAND_Driver

Regards,

Pavel

Hi Pavel.

Thank you for reply.

We are using the latest version EZSDK 5.05.
Your reference refer to NAND performance in kernel. I the kernel NAND flash works quite fast.
I want to drow your attention that the problem with NAND performance in u-boot.

Some additional information. In our device we are using Samsung SLC NAND Flash (8bit data bus).

Best Regards, Evgeny Kvashnin.

Evgeny,

You can optimize the NAND driver in u-boot to get good speeds of the range 10MB/sec.