Max HRDY latency

Daniele,

The HPI port is designed with the intention that you use the HRDY signal for its intended purpose instead of designing in a timeout to save one pin or a small amount of logic.

The maximum time HRDY could be high is indeterminate. If the HRDY access were reading from some location that other bus masters are also accessing, the HRDY access could be stalled behind those until they complete. This will usually be a small amount of time, but it will vary depending on the total system load, and that system load depends on what your system is doing.

It can also depend on what you are doing with the HPI port. If you have sent a lot of HPI writes, then start to read from the same addresses, there could be a greater stall time behind the completion of those writes before the read could complete.

So I hope you can see that it is not possible to specify a maximum delay for HRDY.

Regards,
RandyP

Hi RandyP,

If the master priority for the HPI is higher than other masters, can the delay for HRDY be estimated in the worst case?

Best regards,

Daisuke

Hi RandyP,

Daisuke Maeda said:

If the master priority for the HPI is higher than other masters, can the delay for HRDY be estimated in the worst case?

The estimate does not have to be correct.
Is it more than several microseconds?

Best regards,

Daisuke

Daisuke,

I would like to say the delay would typically be 10's of cycles and worst case 100's of cycles. But I cannot say that about any unknown system because there could be external factors that make the delay longer.

You would need to analyze your system and how your system is accessing the same memory or peripheral components that the HPI is accessing. You could run your system 100's of times and measure the longest delay on HRDY to get a reasonable idea of typical delays, but it is still possible that some other circumstances occur only once per day or once per week or even less often, and one situation could then cause your system to crash.

Like the calculation of Bit Error Rates in communication channels, there is a probability associated with a longer HRDY delay. You might never see it happen, or you might see it often or rarely. If you choose any maximum delay, you will be setting a probability point at which you could get an error in a rare case.

The only true solution is to use the HRDY pin as designed. Any other method that bypasses it adds a risk of failure to your system.

Regards,
RandyP

Hi RandyP,

Thank you for your reply.

About the "cycles" which you said, is it the HCS clock cycles?

Can it be predicted about the cycles of the longer HRDY delay that may be seen often or rarely?
If the cycles of delay is not allowed for the system, the HRDY pin must be used.

Best regards,

Daisuke

Daisuke,

Daisuke Maeda said:

About the "cycles" which you said, is it the HCS clock cycles?

I was thinking DSP clock cycles. But since the counts are vague and cannot be stated, the scale of the clocks will not affect the answer.

Daisuke Maeda said:

Can it be predicted about the cycles of the longer HRDY delay that may be seen often or rarely?

No, I cannot predict this.

Daisuke Maeda said:

If the cycles of delay is not allowed for the system, the HRDY pin must be used.

The HPI was designed to use the HRDY pin.

Regards,
RandyP