Disabling DDR/MSMC L2 caching

There are two inline functions to disable and enable parts of the cache

Look at the file csl_cacheAux.h in pdk directory that you use at   packages\ti\csl for this file:

CSL_IDEF_INLINE void CACHE_enableCaching  (Uint8 mar)
{
    CSL_FINS(hCache->MAR[mar], CGEM_MAR0_PC, 1);
}

 * =============================================================================
 */
CSL_IDEF_INLINE void CACHE_disableCaching (Uint8 mar)
{
    CSL_FINS(hCache->MAR[mar], CGEM_MAR0_PC, 0);
}

The MAR register is defined in table 4-20 of the CorePac user guide.  I have SPRUGW0A November 2010 version.  In a newer version the table might move.  The table name is Memory Attribute Registers

The table gives the memory region for each one of the 256 MAR registers

You can see  logical names in the file cslr_cgen.h at the same directory 

Ran

These functions do not write to the memory address for me. Where is CGEM_MAR0_PC defined?

You can try and look at the release and find where it is defined.

For 6678 the base address of the MAR registers is 0x01848000   you can find it in      SPRUGW0B     Page 4-20   

The following code explicitly disables cache and prefetch.  My example use MAR 144 and MAR 145  (addresses 0x9000 0000 and 0x9100 0000

volatile uint32_t* lvMarPtr;

//////////////////////////////////////////////////////////////////////////////

//   Ran Katzur comment - disable cache from local memories

lvMarPtr = ( volatile uint32_t*)0x01848240; //  This is MAR 144

*lvMarPtr = 0;  //    disable cache and prefetch.  If you want to keep prefetch look at the definition of the MAR registers (next table in the document) 

//  the location of MAR 145

lvMarPtr = ( volatile uint32_t*)0x01848244   ;

*lvMarPtr = 0;  ;