OMAP-L138: pinout question

Hi Paul

EMA_A[23] has now been "undocumented" from the datasheet because it does not serve any purpose. A23 would have provided upto 64 MB addressable space per chip select, unfortunately on this device family per CS space is upto 32MB from the memory map design perspective.

So although this pin is physically available, it has no use on the device family and therefore to remove confusion we removed it from the datasheet. Ideally this should've been removed from the symbol map and pinmux tool too, I will see what we can do get these things at par with the datasheet to avoid confusion.

Hope this helps.

Regards

Mukul

Thanks for the feedback Mukul!  Very much appreciated!

I am afraid that I am still a bit confused.  I am calculating that to address 32 Mbytes of memory one needs 25 address lines, A0 through A24.  Assuming that BA1 takes the place of A0, then the EMIF A0 – A22 become A1 – A23.  This still leaves me short one address line.  Unless what is really happening is that the BA0 and BA1 become A0 and A1 so that the rest of the address bus become A2 – A24.  Is this what is happening or have I managed to slip a few powers of 2 and made a mess?  Thanks again for the help!

Paul

You are on the right track with BA0 and BA1 usage, the EMIF user guide and this helpful wiki article from Brad Griffis should help clarify further

I found that TI has an unconventional way of labelling the address pins. I first assumed that since I was connecting to a 32 bit wide device, that I would connect EMIF_A2 to the lowest significant address line of the device. EMIF_A0 really maps to A2 on the internal address bus. I think the internal address lines maps to the EMIF pins and 8,16,32 bit devices like so:

A24 -> EMIFA_A22 -> DEV8_A24 -> DEV16_A23-> DEV32_A22
...
A2  -> EMIFA_A0  -> DEV8_A2  -> DEV16_A1 -> DEV32_A0
A1  -> EMIFA_BA1 -> DEV8_A1  -> DEV16_A0
A0  -> EMIFA_BA0 -> DEV8_A0

The mapping does not shift around. A2 is always EMIFA_A0. So you have to increment your address by 4 before EMIFA_A0 will change by one. Assuming your address is initially quad byte aligned.

EDIT: Correct typos.

Thanks very much!

I think that I have gotten the Flash connected properly.  Now I am trying to connect a small chunk of SRAM as a moderately fast and low power scratch pad area.  SDRAM would have more memory that I need and take more power.  I have seen hints of the ability to connect both synchronous and asynchronous SRAM to the OMAP-L138, but so far I have not been able to even find a rough block diagram.  The user guides on TI’s website seem aimed at using various software and operating systems rather than designing hardware.  I would appreciate it if anyone has something that would help here.

Thanks again for all of your help.

Paul