SRIO SGMII HYPERLINK Differential pairs Dynamic phase tolerance

Robert,

Skew matching requirements are well defined within the HW Design guidelines.

Best Regards,
Chad

Hello Chad,

Thank you for the fast response.

I read the HW Design Guidelines. on paragraphs 4.3.2 and  4.3.4 and 4.3.5

I did not see any requirement for dynamic phase control for differential pairs.

Is it written in other place/paragraph ?

OR if it is not written it is not needed ?

Best regards,

Roby

Sorry, I read you post too quickly and missed your specific concern.  I do not believe we have a specific requirement here, but I'll ping one of our board design folks who specialize in this knowledge and have them get back on this.

Best Regards,

Chad

Robert,

The "dynamic phase control" you describe needs to be a concern in all differential routing for gigahertz transmission.  It is not as important below 3GHz but can be very significant at 6GHz and above.  The techniques discussed in the references you sighted should be followed.  Differential signal propagation will be degraded whenever their is length skew along the routed path.

Your final board implementation should be validated through simulation.  You will need to use a tool to extract a model of the routed PCB traces.  This can then be paired with transmitter and receiver models to verify acceptable performance.

Tom

Tom,

i understand that it is recommended for the hyperlink and SRIO - BUT for the SGMII it is not a concern  .

Do you have a general guideline on the best way to implement it ?

For example

1) a short length of after a 90 degree turn of a diff pair i have another 90 degree turn in an opposite direction which eliminates the first turn deskew

in case the two turns are close enough no deskew is needed for both turns - but beyond a specific length between turns each turn should be deskewed

is this length dependent on signal rise time/signal frequency ?

2)the dynamic deskew requires adding extra trace length to the net which is in the inner side of the turn

this extra length changes locally the balanced/symmetrical nature of the differntial structure.(impedance/crosstalk/EMI ... issues )

should the extra length be added as few small addition ? or as one ? any preffered pattern ?

any other recommendation ?

regards,

roby 

Roby,

There are multiple routing techniques that must be followed to reduce loss and optimize signal integrity.  The dynamic deskew for the differential traces is only one of them.  The attached referenceslide set for PCIe routing shows several of these issues on pages 11 through 18.  Additionally, there are various methods for dynamic deskew of routing while avoiding sharp bends.  This presentation that shows a good method for this.

7851.PCIe_designGuides.pdf

Tom

Tom,

Thank you for the document - it is very informative .

The document reminded me two more question regarding the diff pair Dynamic phase control.

1) Diff pair exit from the DSP should also compensate for the internal Electrical pin delay differences

can you send a table with  this info for the TMS320C6678 DSP for all differential interfaces?

2) Do you have any experience with FR4  diff pair skew caused by fiber glass weave effect especially for the hyperlink and SRIO

is it recommended manufacturing the board with a slight rotation angle relative to the orthogonal weave pattern ?

Regards,

Roby

Roby,

The differential pair routing in the package is well controlled.  We do not provide internal routing lengths.  The package parasitics are comprehended in the models provided for simulation.

Fiberglas weave is one of the many concerns for the higher operating speeds.  The differences in the dielectric constant of the fibers versus the resin do impact signal propagation.  Yes you should be concerned about this.  Common techniques include routing on a bias or offsetting routes every inch or so.  Also be sure to use a low-loss enhanced FR4 material.  Standard FR4 is not recommended for the higher operating speeds due to loss.

Tom