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DM814x McASP and EDMA interrupt

Andrew Elder
Expert 1680 points

I'm running McASP through EDMA on the 674+.

EDMA seems like it is running ok. I see the counters running etc. But code to run a HWI is not running for some reason.

I can see events in the EDMA Interrupt Pending Register.

I have created an interrupt using Hwi_create(). I  was wanting to examine the Event Flag Registers next, but I can't seem to find the address for them in the DM814x datasheet (or the TRM for that matter). Should I be looking somewhere else ?

  • 0
    TI__Guru**** 170625 points

    hi Andrew,

    The base address of the EDMA Channel Controller is given in the DM814x DataSheet: 0x49000000 (for L3 access) and 0x09000000 (for DSP access).

    The offset of the Event registers (ER and ERH) is given in the DM814x TRM: 0x1000 (ER) and 0x1004 (ERH).

    Thus the full addresses of the ER and ERH registers for L3 access are: 0x49001000 and 0x49001004. 

    The full addresses of the ER and ERH register for DSP access are: 0x09001000 and 0x09001004.

    Best regards,

    Pavel

  • 0 in reply to Pavel Botev
    Expert 1680 points

    Hi Pavel,

    Perhaps I wasn't clear. I can see the EDMA CC ok. And I see bits set in the Interrupt Pending Register (IPR), so I have concluded that the EDMA TC event has been processed from the ER to the IPR. What I can't figure out is where to check after the IPR bits are set. I assume the interrupt controller event register, correct ? It is the interrupt controller event register that I can't seem to find the address of.

    - Andrew

  • 0 in reply to Andrew Elder
    TI__Guru**** 170625 points

    hi Andrew,

    The base address of the Cortex-A8 Interrupt Controller is 0x48200000. The Cortex-A8 Interrupt Controller registers description and offsets are in TRM, table 14-3.

    Please have a look also on this forum subject: http://e2e.ti.com/support/embedded/bios/f/355/t/133768.aspx

    Best regards,

    Pavel

  • 0 in reply to Pavel Botev
    Expert 1680 points

    Hi Pavel,

    Yes, I saw that other post earlier in my research. McASP, EDMA and HWI are all being configured to run on 674+. So interrupts would not go through the ARM AINTC controller (as you suggest above) would they ?

    Perhaps it is incorrect to "care' whether the DSP or ARM configured the McASP and EDMA as they share SoC resources ?

    Section 14 Interrupt Controller in TRM is dedicated to the Cortex-A8 interrupt controller. Is that incorrect ? Is the implication that all interrupts go through the AINTC controller ?

    I'll do some more reading today and see where I get to. I'll post some code if I can't figure it out.

    - Andrew

  • 0 in reply to Andrew Elder
    Expert 1680 points

    Looking at Figure 8-14 Interrupt Diagram in Section 8.4.9.1.1 Enabling Transfer Completion Interrupts in the DM814x TRM, I can't seem to find EDMA3CC_INT1 signal/flag/event anywhere in the TRM or datasheet. Am I missing something ? I would have expected to see it in the interrupt event list in the datasheet.

    I am using EDMA shadow region 1.

  • 0 in reply to Andrew Elder
    Expert 1680 points

    Ok, I got it to work. The HWI was actually firing, but a callback routine that I thought would be working for sure wasn't running. One point that is sort of buried in the TRM is that EDMA interrupts on the DSP use shadow region 1. See section 1.6.2 in the TRM. So the EDMA3CC_INT1 described in section 8.4.9 of the TRM where it discusses how different shadow regions produce different interrupts should really state that the user needs to find which of the shadow region's map to what processor. Or, better yet, the datasheet interrupt section should list EDMA region interrupt -> core mapping.

  • 0 in reply to Andrew Elder
    TI__Guru**** 170625 points

    Hi Andrew,

    I am glad you solve your issue, and I will report your documentation enhancement proposal to the TRM team.

    Best regards,

    Pavel