Chip Support Library PLL Configuration question

Todd,

Todd Anderson78572 said:

Can someone tell me what each of the 4 parameters represents?

These are the various Clock Generator registers. Below is some sample code from my PLL init routine. See the comments. You can verify this by running the CSL example code and single stepping through the PLL_config() function. 

#if (PLL_120M ==1)
PLL_CNTL2 = 0x8000; //CGCR2 (input/reference divider) RDRATIO + 4
PLL_CNTL4 = 0x0000; //CGCR4 (output divider) ODRATIO + 1
PLL_CNTL3 = 0x0806; //CGCR3 fixed
PLL_CNTL1 = 0x8E4B; //CRCR1 PLL Multiplier + 4

Unfortunately, as with most of the C55xx CSL, the documentation is horrible and outdated.

Take a look at SPRUFX5D starting in section 1.3, Device Clocking.

I hope this helps .

The definition of the data structure PLL_Config is in <CSL_INSTALL_DIR>\c55xx_csl\inc\csl_pll.h.  How these parameters correspond to registers of the PLL are in the PLL_Config() API implementation itself found in <CSL_INSTALL_DIR>\c55xx_csl\src\csl_pll.c.

typedef struct {
  Uint16    PLLCNTL1;
  Uint16    PLLINCNTL;
  Uint16    PLLCNTL2;
  Uint16    PLLOUTCNTL;
} PLL_Config;

CSL_Status PLL_config(PLL_Handle hPll, PLL_Config *pconfigInfo)
{
...
    hPll->sysAddr->CGICR = pconfigInfo->PLLINCNTL;
    hPll->sysAddr->CGOCR = pconfigInfo->PLLOUTCNTL;
    hPll->sysAddr->CGCR2 = pconfigInfo->PLLCNTL2;
...
#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
    hPll->sysAddr->CGCR1 |= ((CSL_SYS_CGCR1_VP_MASK | CSL_SYS_CGCR1_VS_MASK) & pconfigInfo->PLLCNTL1);
#else
    hPll->sysAddr->CGCR1 |= (CSL_SYS_CGCR1_MH_MASK & pconfigInfo->PLLCNTL1);
#endif
...
}