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AM335x DDR PHY register configuration

Hi,


This is regarding the AM335x DDR PHY register configuration.

Is it required to do the "Software Leveling procedure" mentioned in the Wiki page below.
http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

Our customer has found out Optimum values through a manual procedure and
wants to know whether "Software Leveling procedure" really required for their custom board with DDR3?

And if possible could you please let us know briefly what kind of procedure
is done with the "DDR3_slave_ratio_search_auto.out" program.


Regards.
Paddu

  • The software leveling procedure is just a tool for the customer to use to determine the optimum values.  If they have done this another way then that is fine.  Although i'd be interested in what procedure they took. The CCS program simply iterates on a number of tests to determine the timing window of several signals in which successful accesses can be made to the SDRAM. 

    Regards,

    James

  • James,

    Thank you so much for the quick reply.
    I shall come back to you with the details of our customer's procedure.
    Meanwhile, I was curious to know if source code of "DDR3_slave_ratio_search_auto.out"
    is available public.

    Regards
    paddu.

  • The source code is not available publicly

    Regards,

    James

  • Hi,

    Sorry for the delay,
    it seems our customer doesn't hav any procedure and the DDR3 seems
    to be working on their EVM without doing any software leveling.
    But we have recomended them to use the "software leveling" procedure.

    "DDR3_slave_ratio_search_auto.out" program seems to be used on DM814x
    also, is this program tested on the upcoming AM335x EVM?
    and please let us know if there is any possiblity to send us the source code,
    as our customer is interested to know more about the program.


    Regards.
    paddu