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C6678 SPI RX Interrupt triggering only once

Hi,

We have a C6678-based custom design which require the use of the SPI-module in the DSP, and have developed a interrupt based driver for it that uses the SPI Receiver full interrupt on SPI interrupt line 0. But we are struggling  to make this work correctly. A debug counter in the interrupt handler only counts a single interrupt, even if multiple transfers are done on the SPI bus. The driver makes sure that the RX interrupt flag is cleared before leaving the interrupt handler function.

The following XDC script setup is used for the c66.tci66xx.CpIntc module: 

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/* SPI interrupt line */
CpIntc.sysInts[54].fxn = '&dspspi_line0isr'; // Handler for system interrupt #54 (SPI interrupt 0 )
CpIntc.sysInts[54].arg = 0x42;               // Argument for function. 
CpIntc.sysInts[54].hostInt = 34;             // CorePac system event number 23
CpIntc.sysInts[54].enable = true;            // Enable the system interrupt

CpIntc.mapHostIntToHwiMeta(34, 9);

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Inspecting the registers in the Chip-level Interrupt Controller has revealed that the interrupt is still set in the System Interrupt Status Enabled/Raw registers after the CpIntc interrupt dispatcher has finished. Should the RX interrupt flag be cleared in the SPI module before clearing the system interrupt status? And how can we prevent lost interrupts then ? (In the case where a new RX interrupt is triggered by the SPI module between the clearing of the RX interrupt flag in the SPI module and clearing the system interrupt )

During this debugging process the code in the CpIntc dispatch function has been reviewed, and it appears not to match with the recommendations in  the Chip-level interrupt controller user guide (sprugw4a 1.3.6 Interrupt service sequencing) as host interrupts are not disabled during interrupt clearing and processing. (BIOS version  6.33.05.46).

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Kjetil 

 

 

  • Kjetil,

    I see your point about disabling the host interrupt. Since you have the CpIntc source code, can you please try disabling the host interrupt then re-enabling it to see if that solves your problem?

    I would do on line 163:   CpIntc_disableHostInt(id, hostInt);

    Then on line 207:  CpIntc_enableHostInt(id, hostInt);

    I think its correct for us to clear the system interrupt before calling your function.

    Let me know if this solves your problem.

    Judah

  • Hi Judah,

     With this change too many interrupts are generated. Meaning that the interrupt handler is called with the interrupt vector register in the SPI module indicating that no interrupt was pending. Looking at the debug counters in the interrupt handler also confirms this as the interrupt handler is called twice even if just a single byte was transmitted on the bus.  

     -

    Kjetil 

  • Kjetil,

    So you are saying that when you add the code to disable the host interrupt, then you get 2 interrupts generated where you expect to get only 1 interrupt?  But without the disable host interrupt code, you get 1 interrupt then you can't get another interrupt to be generated?

    1.  I'm not quite following the statement "too many interrupts are generated".  I thought the original problem was that you weren't getting a second interrupt as you would expect.  Is your own interrupt being masked off while processing your interrupt?  This should be the default BIOS behaviour.  The IER should be disabled for your particular interrupt when you are processing it.

    Judah

  • Hi Judah,

     Sorry about the slow response.

    Without this modification to the dispatch code only a single RX interrupt is generated.

     With this modification I get more interrupts than I expect. I.E. If I do a single transaction on the SPI Bus I get two RX interrupts. If I do several back to back transactions. I get the number of expected interrupts+1. 

    I suspect that the following is occurring (without the modification):

    1. The RX interrupt triggers the dispatch function.

    2. The dispatch function clears the interrupt in the chip level interrupt controller. But since the RX interrupt flag is not cleared in the SPI module yet, the interrupt is immediately relatched in the chip level controller. (And as mentioned in the Chip Level Interrupt Controller documentation, any interrupt reoccurring in the same cycle as the interrupt register is cleared will not generate a new interrupt pulse toward the CPU).

    3. My interrupt handler is called, which clears the RX flag by reading the reading the received data, and returns to the dispatch function.

    4. The dispatch function exits with the interrupt flag for SPI RX still set in the Chip Level Interrupt Controller, since it was immediatly relatched after clearing. And the RX interrupt can therefore not retrigger the interrupt dispatcher.

     

    With the modification to the dispatch function:

    1. The RX interrupt triggers the dispatch function.

    2. The host interrupt is cleared/disabled. 

    2. The dispatch function clears the interrupt in the chip level interrupt controller. But since the RX interrupt flag is not cleared in the SPI module yet, the interrupt is immediately relatched in the chip level controller. (And as mentioned in the Chip Level Interrupt Controller documentation, any interrupt reoccurring in the same cycle as the interrupt register is cleared will not generate a new interrupt pulse toward the CPU).

    3. My interrupt handler is called, which clears the RX flag by reading the reading the received data, and returns to the dispatch function.

    4. The host interrupt is reenabled,  and since the interrupt flag in the Chip-Level interrupt controller is still set, it generates a new interrupt pulse towards the CPU. 

    5. The interrupt dispatch function is therefore immediately retriggered.  

    6. The dispatch function clears the interrupt in the chip level interrupt controller. And since the RX interrupt flag was cleared by the previous call to the SPI RX interrupt handler, it is now able to clear it without immediatly relatching the RX interrupt.

    7. My RX interrupt handler is called, but there is no interrupt information present in the SPI module interrupt vector registers, since this isn't a proper interrupt request and return to the dispatcher function.

    8.  The interrupt dispatch function returns, with the SPI RX interrupt cleared in both the SPI module and in the Chip-Level interrupt Controller. It can therefore be retriggered by the SPI module.

    -

    Kjetil 

  • Kjetil,

    I can fix the disable of the host interrupt in the CpIntc dispatch function but as far as your problem with the extra interrupt being generated, I don't know any specifics about SPI or how that can be solved.  I think this thread may need to be moved to a hardware specific forum so that someone with knowledge of the hardware can jump in.

    Judah

  • hi , could you tell me how to config the spi registers, i mean i can not write a value into the register, what should.i do ,thank you