Hi,
We have a C6678-based custom design which require the use of the SPI-module in the DSP, and have developed a interrupt based driver for it that uses the SPI Receiver full interrupt on SPI interrupt line 0. But we are struggling to make this work correctly. A debug counter in the interrupt handler only counts a single interrupt, even if multiple transfers are done on the SPI bus. The driver makes sure that the RX interrupt flag is cleared before leaving the interrupt handler function.
The following XDC script setup is used for the c66.tci66xx.CpIntc module:
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/* SPI interrupt line */
CpIntc.sysInts[54].fxn = '&dspspi_line0isr'; // Handler for system interrupt #54 (SPI interrupt 0 )
CpIntc.sysInts[54].arg = 0x42; // Argument for function.
CpIntc.sysInts[54].hostInt = 34; // CorePac system event number 23
CpIntc.sysInts[54].enable = true; // Enable the system interrupt
CpIntc.mapHostIntToHwiMeta(34, 9);
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Inspecting the registers in the Chip-level Interrupt Controller has revealed that the interrupt is still set in the System Interrupt Status Enabled/Raw registers after the CpIntc interrupt dispatcher has finished. Should the RX interrupt flag be cleared in the SPI module before clearing the system interrupt status? And how can we prevent lost interrupts then ? (In the case where a new RX interrupt is triggered by the SPI module between the clearing of the RX interrupt flag in the SPI module and clearing the system interrupt )
During this debugging process the code in the CpIntc dispatch function has been reviewed, and it appears not to match with the recommendations in the Chip-level interrupt controller user guide (sprugw4a 1.3.6 Interrupt service sequencing) as host interrupts are not disabled during interrupt clearing and processing. (BIOS version 6.33.05.46).
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Kjetil