How to configure vendor specific data in AIF2 Interface for CPRI

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 *           Copyright (C) 2009 Texas Instruments Incorporated.             *
 *                           All Rights Reserved                            *
 *                                                                          *
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 * any incidental, special or consequential damages that result from the    *
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 ****************************************************************************
 *                                                                          *
 * Written by :                                                             *
 *            Albert Bae                                                    *
 *            Texas Instruments                                             *
 *            02 Dec, 2010                                                  *
 *This example shows how to transfer AxC data and CPRI control word together                                                                           *
 ***************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <c6x.h>
#include <ti/csl/src/intc/csl_intc.h>

#include "Aif2_config.h"
#include "psc_util.h"

/* Define queues for common FDQs */
#define MONO_TX_COMPLETE_Q     2000
#define MONO_RX_FDQ            2001

/* These are for the AIF test */
#define MONO_RX_Q              900
#define MONO_TX_Q              512+124 //for control word channel 0

//Users should use 16 bytes aligned data for Aif2 and PktDMA test
#pragma DATA_SECTION(mono_region,".intData_sect")//use MSMC memory for test mode
#pragma DATA_ALIGN (mono_region, 16)
Uint8   mono_region[32 * 716];//payload size is 704 bytes for CPRI control word FastC&M
Uint32  tmp;

//Users should use 16 bytes aligned(Quad word) data for Aif2 and PktDMA data flow
#pragma DATA_ALIGN (dio_data, 16)
Uint32   dio_data[96];
#pragma DATA_ALIGN (dio_result, 16)
Uint32   dio_result[96];

/* Intc variable declarartion */
CSL_IntcObj    intcObj;
CSL_IntcHandle   hIntc;
CSL_IntcEventHandlerRecord  EventHandler[8];
CSL_IntcGlobalEnableState state;

/* Global structures and variables  */
CSL_Aif2Obj Aif2Obj;// Aif2 CSL object
CSL_Aif2Handle hAif2;// Aif2 handle 
Bool ctrlArg; // Ctrl Argument;

CSL_Aif2Context Aif2Context;//Aif2 context
CSL_Aif2Param  aif2Param;//AIF2 module specific parameters
CSL_Status status; // CSL status
   
CSL_Aif2Setup               aif2Setup;//Aif2 HW setup
CSL_Aif2LinkSetup           linkSetup;// Setup for links 
CSL_Aif2GlobalSetup         globalSetup;// global config for AIF2 
CSL_Aif2CommonSetup         commonSetup; // Setup for common params
   
CSL_Aif2SdCommonSetup       SdCommonSetup;//SERDES common setup
CSL_Aif2PdCommonSetup       PdCommonSetup;//PD common setup
CSL_Aif2PeCommonSetup       PeCommonSetup;//PE common setup
CSL_Aif2IngrDbSetup         IngrDbSetup;// Ingress data buffer setup 
CSL_Aif2EgrDbSetup          EgrDbSetup;// Egress data buffer setup 
CSL_Aif2AdCommonSetup       AdCommonSetup;// Aif2 DMA common setup 
CSL_Aif2AdDioSetup          AdDioSetup;// Aif2 DIO common setup 
CSL_Aif2AtCommonSetup       AtCommonSetup; // Aif2 Timer common  setup 
CSL_Aif2AtEventSetup        AtEventSetup; // Aif2 Timer external and internal event  setup 
CSL_Aif2AtCountObj          PhyTimerTc;// AT Phy Terminal Count setup
CSL_Aif2AtCountObj          RadTimerTc;// AT Rad Terminal Count setup
CSL_Aif2AtCountObj          PhyTimerInit;// AT Phy Init value setup
CSL_Aif2AtCountObj          RadTimerInit;// AT Rad Init value setup
CSL_Aif2AtCountObj          UlRadTimerInit;// AT Rad Init value setup
   
CSL_Aif2CommonLinkSetup     ComLinkSetup; // Aif2 link common setup 
CSL_Aif2SdLinkSetup         SdLinkSetup; //SERDES link setup
CSL_Aif2RmLinkSetup         RmLinkSetup; //RM link setup
CSL_Aif2TmLinkSetup         TmLinkSetup; //TM link setup
CSL_Aif2PdLinkSetup         PdLinkSetup; //PD link setup
CSL_Aif2PeLinkSetup         PeLinkSetup; //PE link setup
CSL_Aif2RtLinkSetup         RtLinkSetup; //RT link setup
CSL_Aif2AtLinkSetup         AtLinkSetup; // Aif2 timer link setup (Pi, Delta, PE signal) 

extern void Start_timer0(void);
volatile unsigned int int4_result;

interrupt void int4_isr(){
	  
	  tmp = pop_queue(MONO_TX_COMPLETE_Q);
      tmp &= 0xFFFFFFF0;//set DESC_SIZE field to zero
      
      tmp |= 0x00000003;//set DESC_SIZE to 3 for AIF2 mono mode
      push_queue(MONO_TX_Q, 1, 0, tmp);
	  
      int4_result++;
}

void Intc_config(void)
{
   CSL_IntcParam    vectId;
   CSL_IntcContext  context;
   //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
   //! GEM0 Intc Configuration              !//
   //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
   /* Setup the global Interrupt */
   context.numEvtEntries = 8;    
   context.eventhandlerRecord = EventHandler; 
   CSL_intcInit(&context);
   /* Enable NMIs  */
   CSL_intcGlobalNmiEnable();
   /* Enable Global Interrupts  */
   CSL_intcGlobalEnable(&state);
   
   /* VectorID for the Global Edma Event  */
   vectId = CSL_INTC_VECTID_4;
   
   /* Opening a handle for the Fsync->EDMA Interrupt Event */                                      
   hIntc   = CSL_intcOpen(&intcObj,
                           AIF2_EVENT0_INTSEL_MAP, // Event0
                           &vectId,
                           NULL);
   //Hook the ISRs
   CSL_intcHookIsr(vectId,  &int4_isr);
   // Clear the Interrupt    
   CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTCLEAR,  NULL);
   //Enable the Event & the interrupt 
   CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTENABLE,  NULL);
}

void MNavigator_config(void)
{
	Uint32  flow_a, flow_d, i;
    Uint16  idx;
    Uint32 *temp;
    MNAV_MonolithicPacketDescriptor *mono_pkt;

   /* Setup Memory Region 0 for 32 720B Monolithic descriptors. Our
    * Mono descriptors will be 12 bytes, plus 704 bytes of payload(FastC&M). 
    * so the total size should be 720 to dividable by 16 * 32 descriptors. */
    set_memory_region(0, (Uint32) mono_region, 0, 0x002C0000);

   /*****************************************************************
    * Configure Linking RAM 0 for the descriptor regions.
    */
   set_link_ram(0, QM_LRAM_REGION, 0x3fff); //internal link ram

    /* Initialize descriptor regions to zero */
    memset(mono_region, 0, 32 * 720);

    /* Push 8 Monolithic packets into Tx Completion Queue */
    for (idx = 0; idx < 8; idx ++)
    {
      mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 720));
      mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
      mono_pkt->data_offset = 12;
      mono_pkt->pkt_return_qmgr = 0;
      mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q; 
      mono_pkt->packet_length = 704;
      mono_pkt->ps_flags = 0; 
      mono_pkt->epib = 0;
      mono_pkt->psv_word_count = 0; 
      mono_pkt->src_tag_lo = 124; //copied to .flo_idx of streaming i/f
      
      temp = (Uint32 *)(mono_region + (idx * 720) + 12);
      for (i = 0; i< 176;i++)temp[i] = i; 
      
      push_queue(MONO_TX_COMPLETE_Q, 1, 0, (Uint32)(mono_pkt));
    }

    /* Push 8 Monolithic packets to Rx FDQ  */
    for (idx = 16; idx < 24; idx ++)
    {
      mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 720));
      mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
      mono_pkt->data_offset = 12;
      mono_pkt->pkt_return_qmgr = 0;
      mono_pkt->pkt_return_qnum = MONO_RX_FDQ; 
      
      push_queue(MONO_RX_FDQ, 1, 0, (Uint32)(mono_pkt));
    }
    
   /*****************************************************************
    * Configure Rx channel flows  */
    //Create flow configuration 0 for the Monolithic packets
    flow_a = 0x080C0000 | MONO_RX_Q;
    flow_d = MONO_RX_FDQ << 16;
    config_rx_flow(AIF_PKTDMA_RX_FLOW_REGION, 124,
                   flow_a, 0, 0, flow_d, 0, 0, 0, 0);

   /*****************************************************************
    * Enable Packet Tx and Rx channel for CPRI control word*/
    enable_disable_loopback(0);//disable PKTDMA loopback 
    enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 124, 0x80000000);
    enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, 124, 0x80000000);
    
    /* Enable DIO Tx and Rx channels. (channel 128 for DIO)**/
    enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 128, 0x80000000);
    enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, 128, 0x80000000);
}

void Aif2_Dio_Cpri_Rac_config(void)
{   
   int i;
   //////////////////Initialize Aif2 structures to avoid unwanted configuration ////////////////////////////////////////
   memset(&globalSetup, 0, sizeof(globalSetup));
   memset(&linkSetup, 0, sizeof(linkSetup));
   memset(&commonSetup, 0, sizeof(commonSetup));
   
   memset(&SdCommonSetup, 0, sizeof(SdCommonSetup));
   memset(&PdCommonSetup, 0, sizeof(PdCommonSetup));
   memset(&PeCommonSetup, 0, sizeof(PeCommonSetup));
   memset(&IngrDbSetup, 0, sizeof(IngrDbSetup));
   memset(&EgrDbSetup, 0, sizeof(EgrDbSetup));
   memset(&AdCommonSetup, 0, sizeof(AdCommonSetup));
   memset(&AdDioSetup, 0, sizeof(AdDioSetup));
   memset(&AtCommonSetup, 0, sizeof(AtCommonSetup));
   memset(&AtEventSetup, 0, sizeof(AtEventSetup));
   memset(&PhyTimerInit, 0, sizeof(PhyTimerInit));
   memset(&RadTimerInit, 0, sizeof(RadTimerInit));
   memset(&UlRadTimerInit, 0, sizeof(UlRadTimerInit));
   memset(&PhyTimerTc, 0, sizeof(PhyTimerTc));
   memset(&RadTimerTc, 0, sizeof(RadTimerTc));
   
   memset(&ComLinkSetup, 0, sizeof(ComLinkSetup));
   memset(&SdLinkSetup, 0, sizeof(SdLinkSetup));
   memset(&RmLinkSetup, 0, sizeof(RmLinkSetup));
   memset(&TmLinkSetup, 0, sizeof(TmLinkSetup));
   memset(&PdLinkSetup, 0, sizeof(PdLinkSetup));
   memset(&PeLinkSetup, 0, sizeof(PeLinkSetup));
   memset(&RtLinkSetup, 0, sizeof(RtLinkSetup));
   memset(&AtLinkSetup, 0, sizeof(AtLinkSetup));
   
   // Initialize CSL library, this step is required 
   CSL_aif2Init(&Aif2Context);
   
   // Open Aif2 and get handle 
   hAif2 = CSL_aif2Open(&Aif2Obj, CSL_AIF, &aif2Param, &status);

   if ((hAif2 == NULL) || (status != CSL_SOK)) 
   {
      printf ("\nError opening CSL_AIF2");
      exit(1);
   }
   
   /////////////////populating AIF2 major setup structures ////////////////////////////////////////////////////////// 
   aif2Setup.globalSetup = &globalSetup;
   aif2Setup.commonSetup = &commonSetup;
   aif2Setup.linkSetup[CSL_AIF2_LINK_0] = &linkSetup;//link setup for link 0
 
   // populate global config fields
   globalSetup.ActiveLink[CSL_AIF2_LINK_0] = TRUE;//Activate link 0 
   globalSetup.frameMode = CSL_AIF2_FRAME_MODE_NORMAL; 
  
   //populate common config fields
   commonSetup.pSdCommonSetup = &SdCommonSetup;
   commonSetup.pPdCommonSetup = &PdCommonSetup;
   commonSetup.pPeCommonSetup = &PeCommonSetup;
   commonSetup.pIngrDbSetup   = &IngrDbSetup;
   commonSetup.pEgrDbSetup    = &EgrDbSetup;
   commonSetup.pAdCommonSetup = &AdCommonSetup;
   commonSetup.pAdDioSetup    = &AdDioSetup;
   commonSetup.pAtCommonSetup = &AtCommonSetup;
   commonSetup.pAtEventSetup  = &AtEventSetup; 
   
   ////////////Link Setup (Do this setup repeatedly with different link setup structure if user wants to use multiple links)////////////
   //populate link config fields for link 0
   linkSetup.linkIndex     = CSL_AIF2_LINK_0; 
   linkSetup.pComLinkSetup = &ComLinkSetup;
   linkSetup.pSdLinkSetup  = &SdLinkSetup;
   linkSetup.pRmLinkSetup  = &RmLinkSetup;
   linkSetup.pTmLinkSetup  = &TmLinkSetup;
   linkSetup.pPdLinkSetup  = &PdLinkSetup;
   linkSetup.pPeLinkSetup  = &PeLinkSetup;
   linkSetup.pRtLinkSetup  = &RtLinkSetup;
   linkSetup.pAtLinkSetup  = &AtLinkSetup;
   
   //Link Common setup
   ComLinkSetup.linkProtocol = CSL_AIF2_LINK_PROTOCOL_CPRI;
   ComLinkSetup.linkRate = CSL_AIF2_LINK_RATE_4x;
   ComLinkSetup.IngrDataWidth = CSL_AIF2_DATA_WIDTH_7_BIT;
   ComLinkSetup.EgrDataWidth = CSL_AIF2_DATA_WIDTH_7_BIT;
   
   //SD link setup
   SdLinkSetup.rxAlign = CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE;
   SdLinkSetup.rxLos = CSL_AIF2_SD_RX_LOS_ENABLE;
   SdLinkSetup.rxCdrAlgorithm = CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_1;
   SdLinkSetup.rxInvertPolarity = CSL_AIF2_SD_RX_NORMAL_POLARITY;
   SdLinkSetup.rxTermination = CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 ;//for AC coupled application
   SdLinkSetup.rxEqualizerConfig = CSL_AIF2_SD_RX_EQ_ADAPTIVE;//Equalizer On
   SdLinkSetup.bRxEqHold = FALSE;//fixed value
   SdLinkSetup.bRxOffsetComp = TRUE;//fixed value
   SdLinkSetup.bEnableTxSyncMater = TRUE; //fixed value
   SdLinkSetup.txInvertPolarity = CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY;
   SdLinkSetup.txOutputSwing = CSL_AIF2_SD_TX_OUTPUT_SWING_14;
   SdLinkSetup.txPrecursorTapWeight = CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2;// -5%
   SdLinkSetup.txPostcursorTapWeight = CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24;// -20%
   SdLinkSetup.bTxFirFilterUpdate = TRUE;//FIR filter update on
   
   //TM link setup
   TmLinkSetup.bEnableTmLink = TRUE;
   TmLinkSetup.bEnableRmLos = FALSE;
   TmLinkSetup.SeedValue = 0x1;
   TmLinkSetup.bEnableScrambler = FALSE;
   TmLinkSetup.pCpriTmSetup.L1InbandEn = 0;//disable 9 bits mask
   TmLinkSetup.pCpriTmSetup.RmLinkLosError = CSL_AIF2_LINK_0;//select link 1 as source RM link
   TmLinkSetup.pCpriTmSetup.RmLinkLofError = CSL_AIF2_LINK_0;//select link 1 as source RM link
   TmLinkSetup.pCpriTmSetup.RmLinkLosRx = CSL_AIF2_LINK_0;//select link 1 as source RM link
   TmLinkSetup.pCpriTmSetup.RmLinkLofRx = CSL_AIF2_LINK_0;//select link 1 as source RM link
   TmLinkSetup.pCpriTmSetup.RmLinkRaiRx = CSL_AIF2_LINK_0;//select link 1 as source RM link
   TmLinkSetup.pCpriTmSetup.TxStartup = 0;
   TmLinkSetup.pCpriTmSetup.TxPointerP = 20;
   TmLinkSetup.pCpriTmSetup.TxProtocolVer = 1;
   
   //RM link setup
   RmLinkSetup.bEnableRmLink = TRUE;
   RmLinkSetup.RmFifoThold = CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY;
   RmLinkSetup.RmErrorSuppress = CSL_AIF2_RM_ERROR_ALLOW;
   RmLinkSetup.bEnableSdAutoAlign = FALSE;
   RmLinkSetup.bEnableScrambler = FALSE;
   RmLinkSetup.bEnableLcvUnsync = FALSE;
   RmLinkSetup.bEnableLcvControl = TRUE;
   RmLinkSetup.bEnableWatchDog = FALSE;
   RmLinkSetup.WatchDogWrap = 0xFF;//set watch dog wrap value
   RmLinkSetup.bEnableClockQuality = FALSE;
   RmLinkSetup.ClockMonitorWrap = 0;
   RmLinkSetup.losDetThreshold = RM_LOS_DET_THOLD;
   RmLinkSetup.SyncThreshold = RM_SYNC_THOLD;
   RmLinkSetup.FrameSyncThreshold = RM_SYNC_THOLD;
   RmLinkSetup.UnsyncThreshold = RM_UNSYNC_THOLD;
   RmLinkSetup.FrameUnsyncThreshold = RM_UNSYNC_THOLD;
   
   //RT link setup
   RtLinkSetup.CiSelect =  CSL_AIF2_LINK_0;
   RtLinkSetup.bEnableEmptyMsg = TRUE;
   RtLinkSetup.RtConfig = CSL_AIF2_RT_MODE_TRANSMIT;// takes PE input only
   
   //PD link setup
   PdLinkSetup.bEnablePdLink = TRUE;
   PdLinkSetup.CpriEnetStrip = 0;
   PdLinkSetup.Crc8Poly = CRC8_POLY;
   PdLinkSetup.Crc8Seed = CRC8_SEED;
   PdLinkSetup.CpriCwNullDelimitor = 0xFB;//K 27.7 charactor
   PdLinkSetup.CpriCwPktDelimitor[0] = CSL_AIF2_CW_DELIM_NULLDELM;
   PdLinkSetup.PdCpriCrcType[0] = CSL_AIF2_CRC_8BIT;
   PdLinkSetup.bEnableCpriCrc[0] = FALSE;//disable CPRI CRC for control channel 0
   PdLinkSetup.PdPackDmaCh[0] = 124;//Set DB channel 124 as a dma ch for control channel 0
   PdLinkSetup.bEnablePack[0] = TRUE;//enable CPRI control channel 0 packing
   
   PdLinkSetup.PdCpriDualBitMap.DbmX = 15;//16 for 4x link speed with 7bit data. set X-1
   PdLinkSetup.PdCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample
   PdLinkSetup.PdCpriDualBitMap.Dbm1Mult = 0;//set n-1
   PdLinkSetup.PdCpriDualBitMap.Dbm1Size = 0;//set n-1
   PdLinkSetup.PdCpriDualBitMap.Dbm1Map[0] = 0x0;
   PdLinkSetup.PdCpriDualBitMap.Dbm2Size = 0;
   PdLinkSetup.PdCpriDualBitMap.Dbm2Map[0] = 0x0;
   for(i=0;i<3;i++)//cpri id lut setup for X position 0,1,2
   {
   PdLinkSetup.CpriDmaCh[i]= i; //DbmX channel num (X position num and DB channel number is same in this test)
   PdLinkSetup.bEnableCpriX[i]= TRUE; //enable CPRI X channel 
   PdLinkSetup.bEnableCpriPkt[i]= FALSE;//use AxC data mode
   PdLinkSetup.Cpri8WordOffset[i]= 0;//more detailed CPRI AxC offset
   }
   for(i=0;i<256;i++)//cpri cw lut setup 
   {
   	  if(((i>= 20)&& (i<64))||((i>= 84)&& (i<128))||((i>= 148)&& (i<192))||((i>= 212)&& (i<256))){
      PdLinkSetup.CpriCwChannel[i]= 0; //set CW sub channel num to pack 0 
      PdLinkSetup.bEnableCpriCw[i]= TRUE; //enable CW sub channel for FastC&M 
   	  }
   }
   PdLinkSetup.bHyperFrameEop[255]= TRUE;//set eop at 255th control slot
   
   //PE link setup
   PeLinkSetup.bEnablePeLink = TRUE;
   PeLinkSetup.PeCppiDioSel = CSL_AIF2_DIO;
   PeLinkSetup.Crc8Poly = CRC8_POLY;
   PeLinkSetup.Crc8Seed = CRC8_SEED;
   PeLinkSetup.PeDelay = DB_PE_DELAY_CPRI;
   PeLinkSetup.PeCpriDualBitMap.DbmX = 15;//16 for 4x link speed with 7bit data. set X-1
   PeLinkSetup.PeCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample
   PeLinkSetup.PeCpriDualBitMap.Dbm1Mult = 0;//set n-1
   PeLinkSetup.PeCpriDualBitMap.Dbm1Size = 0;//set n-1
   PeLinkSetup.PeCpriDualBitMap.Dbm1Map[0] = 0x0;
   PeLinkSetup.PeCpriDualBitMap.Dbm2Size = 0;
   PeLinkSetup.PeCpriDualBitMap.Dbm2Map[0] = 0x0;
   PeLinkSetup.CpriAxCPack = CSL_AIF2_CPRI_7BIT_SAMPLE;
   PeLinkSetup.CpriCwNullDelimitor = 0xFB;//K 27.7 charactor
   PeLinkSetup.CpriCwPktDelimitor[0] = CSL_AIF2_CW_DELIM_NULLDELM;
   PeLinkSetup.PePackDmaCh[0] = 124;
   PeLinkSetup.bEnablePack[0] = TRUE;
   for(i=0;i<256;i++)//cpri cw lut setup
   {
   	  if(((i>= 20)&& (i<64))||((i>= 84)&& (i<128))||((i>= 148)&& (i<192))||((i>= 212)&& (i<256))){
      PeLinkSetup.CpriCwChannel[i]= 0; //set CW sub channel num to pack 0 
      PeLinkSetup.bEnableCpriCw[i]= TRUE; //enable CW Sub channel for Fast C&M
   	  }
   }
  
   //AT link setup
   AtLinkSetup.PE1Offset = 300;
   AtLinkSetup.PE2Offset = 310;
   AtLinkSetup.DeltaOffset = 370;
   AtLinkSetup.PiMin = 370;
   AtLinkSetup.PiMax = 420;
   AtLinkSetup.IsNegativeDelta = FALSE;//positive delta
   
   //////////////////// Common Setup  ///////////////////////////////////////////////////////
   //SD common setup
   SdCommonSetup.bEnablePllB8 = TRUE;
   SdCommonSetup.CLKBYP_B8 = CSL_AIF2_PLL_CLOCK_NO_BYPASS;
   SdCommonSetup.LB_B8 = CSL_AIF2_PLL_LOOP_BAND_MID;//High BW is also fine
   SdCommonSetup.VoltRangeB8 = CSL_AIF2_PLL_VOLTAGE_LOW;//fixed factor
   SdCommonSetup.SleepPllB8 = CSL_AIF2_PLL_AWAKE;
   SdCommonSetup.pllMpyFactorB8 = CSL_AIF2_PLL_MUL_FACTOR_20X;//for CPRI when reference clock is 122.88 Mhz
   SdCommonSetup.SysClockSelect = CSL_AIF2_SD_BYTECLOCK_FROM_B8;
   SdCommonSetup.DisableLinkClock[0] = FALSE;//enable link0 clock
  
   
   //PD common setup
   PdCommonSetup.PdCppiDioSel = CSL_AIF2_DIO;//DIO
   PdCommonSetup.AxCOffsetWin = AXC_OFFSET_WIN;//only used for OBSAI
   PdCommonSetup.PdRadtTC = 2457599;// Radio frame size for CPRI
   PdCommonSetup.PdFrameTC[0].FrameIndexSc = 0;//start index
   PdCommonSetup.PdFrameTC[0].FrameIndexTc = 0;//teminal index
   PdCommonSetup.PdFrameTC[0].FrameSymbolTc = 14;//15 slots for WCDMA
   for(i=0;i<3;i++)//for DB channel 0,1,2
   {
   PdCommonSetup.PdChConfig[i].bChannelEn = TRUE;//Channel enable
   PdCommonSetup.PdChConfig[i].DataFormat = CSL_AIF2_LINK_DATA_TYPE_RSA;//Data format
   PdCommonSetup.AxCOffset[i] = 0;//Ingress AXC offset is not used for CPRI DIO
   PdCommonSetup.PdChConfig1[i].bTsWatchDogEn = FALSE;//disable watchdog 
   PdCommonSetup.PdChConfig1[i].DataFormat = CSL_AIF2_GSM_DATA_OTHER;//Non GSM data
   PdCommonSetup.PdChConfig1[i].FrameCounter = 0;//framing counter group number 
   PdCommonSetup.PdChConfig1[i].DioOffset = 0;//Use zero offset for simple test
   PdCommonSetup.PdChConfig1[i].TddEnable = 0xFFFF;//enables all symbols(FDD) 
   PdCommonSetup.TddEnable1[i] = 0xFFFFFFFF;//enables all symbols(FDD)
   PdCommonSetup.TddEnable2[i] = 0xFFFFFFFF;//enables all symbols(FDD)
   PdCommonSetup.TddEnable3[i] = 0xFFFFFFFF;//enables all symbols(FDD)
   PdCommonSetup.TddEnable4[i] = 0xFFFFFFFF;//enables all symbols(FDD)
   }
   PdCommonSetup.PdChConfig[124].bChannelEn = TRUE;//Control DB Channel enable
   PdCommonSetup.PdChConfig[124].DataFormat = CSL_AIF2_LINK_DATA_TYPE_NORMAL;//Control channel Data format
   
   PdCommonSetup.PdFrameMsgTc[0] = 639; // 640 CPRI quad samples (16 byte) are in  WCDMA slot time
   
   //PE common setup
   PeCommonSetup.PeTokenPhase = 0;//Phase alignment for scheduling DMA
   PeCommonSetup.EnetHeaderSelect = 0;//bit order for Ethernet preamble and SOF 
   PeCommonSetup.GlobalDioLen = CSL_AIF2_DB_DIO_LEN_128;
   PeCommonSetup.PeFrameTC[0].FrameIndexSc = 0;//start index
   PeCommonSetup.PeFrameTC[0].FrameIndexTc = 0;//teminal index
   PeCommonSetup.PeFrameTC[0].FrameSymbolTc = 14;//Set 14 for WCDMA
   for(i=0;i<3;i++)//for channel 0,1,2
   {
   PeCommonSetup.bEnableCh[i] = TRUE;//Enable PE channel
   PeCommonSetup.PeDmaCh0[i].bCrcEn = FALSE;//disable CRC
   PeCommonSetup.PeDmaCh0[i].FrameTC = 0;//use framing terminal count 0
   PeCommonSetup.PeDmaCh0[i].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option
   PeCommonSetup.PeDmaCh0[i].CrcType = CSL_AIF2_CRC_8BIT;//CRC type
   PeCommonSetup.PeDmaCh0[i].isEthernet = FALSE;//AxC data 
   PeCommonSetup.PeInFifo[i].SyncSymbol = 0;//Sync symbol offset
   PeCommonSetup.PeInFifo[i].MFifoWmark = 2;//Message FIFO water mark
   PeCommonSetup.PeInFifo[i].MFifoFullLevel = 3;//Message FIFO full level
   PeCommonSetup.PeAxcOffset[i] = 310;//same to PE2 offset
   }
   PeCommonSetup.bEnableCh[124] = TRUE;//Enable Control channel
   PeCommonSetup.PeDmaCh0[124].bCrcEn = FALSE;//disable CRC
   PeCommonSetup.PeDmaCh0[124].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option
   PeCommonSetup.PeDmaCh0[124].isEthernet = FALSE;
   PeCommonSetup.PeInFifo[124].MFifoWmark = 2;//Message FIFO water mark
   PeCommonSetup.PeInFifo[124].MFifoFullLevel = 3;//Message FIFO full level
   
   PeCommonSetup.PeFrameMsgTc[0] = 2559;//2560 CPRI samples (4 byte) are in  WCDMA slot time
   
   //PE Channel LUT setup and link routing selection (ChIndex number is matched with link number)
   PeCommonSetup.ChIndex0[0] = 0; //channel 0 
   PeCommonSetup.bEnableChIndex0[0] = TRUE;//Route egress channel 0 dbm rule to link0
   PeCommonSetup.CpriPktEn0[0] = FALSE;
   PeCommonSetup.ChIndex0[1] = 1; //channel 1
   PeCommonSetup.bEnableChIndex0[1] = TRUE;//Route egress channel 1 dbm rule to link0
   PeCommonSetup.CpriPktEn0[1] = FALSE;
   PeCommonSetup.ChIndex0[2] = 2; //channel 2
   PeCommonSetup.bEnableChIndex0[2] = TRUE;//Route egress channel 2 dbm rule to link0
   PeCommonSetup.CpriPktEn0[2] = FALSE;
   
   //Ingress DB setup
   IngrDbSetup.bEnableIngrDb = TRUE; //Enable Ingress DB
   IngrDbSetup.DioBufferLen = CSL_AIF2_DB_DIO_LEN_128; //Ingress DB DIO RAM length
   IngrDbSetup.bEnableChannel[0] = TRUE; //Enable Ingress DB channel 0
   IngrDbSetup.IngrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0; //Set DB RAM base address for channel 0
   IngrDbSetup.IngrDbChannel[0].DataSwap = CSL_AIF2_DB_BYTE_SWAP; //For UL
   IngrDbSetup.IngrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   IngrDbSetup.bEnableChannel[1] = TRUE; //Enable Ingress DB channel 1
   IngrDbSetup.IngrDbChannel[1].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_1; //Set DB RAM base address for channel 1
   IngrDbSetup.IngrDbChannel[1].DataSwap = CSL_AIF2_DB_BYTE_SWAP; //For UL
   IngrDbSetup.IngrDbChannel[1].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   IngrDbSetup.bEnableChannel[2] = TRUE; //Enable Ingress DB channel 2
   IngrDbSetup.IngrDbChannel[2].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_2; //Set DB RAM base address for channel 2
   IngrDbSetup.IngrDbChannel[2].DataSwap = CSL_AIF2_DB_BYTE_SWAP; //For UL
   IngrDbSetup.IngrDbChannel[2].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   IngrDbSetup.bEnableChannel[124] = TRUE; //Enable Ingress DB channel 124
   IngrDbSetup.IngrDbChannel[124].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_2 + 4; //Set DB RAM base address for channel 2
   IngrDbSetup.IngrDbChannel[124].DataSwap = CSL_AIF2_DB_NO_SWAP; //No swap
   IngrDbSetup.IngrDbChannel[124].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   
   //Egress DB setup
   EgrDbSetup.bEnableEgrDb = TRUE; //Enable Egress DB
   EgrDbSetup.DioBufferLen = CSL_AIF2_DB_DIO_LEN_128; //Egress DB DIO RAM length
   EgrDbSetup.PmControl = CSL_AIF2_DB_PM_TOKEN_FIFO;//for normal packet performance
   EgrDbSetup.bEnableChannel[0] = TRUE; //Enable Egress DB channel 0
   EgrDbSetup.EgrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0; //Set DB RAM base address for channel 0
   EgrDbSetup.EgrDbChannel[0].DataSwap = CSL_AIF2_DB_BYTE_SWAP; //For UL
   EgrDbSetup.EgrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   EgrDbSetup.EgrDbChannel[0].EgressDioOffset = 0;
   EgrDbSetup.bEnableChannel[1] = TRUE; //Enable Egress DB channel 1
   EgrDbSetup.EgrDbChannel[1].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_1; //Set DB RAM base address for channel 1
   EgrDbSetup.EgrDbChannel[1].DataSwap = CSL_AIF2_DB_BYTE_SWAP; //For UL
   EgrDbSetup.EgrDbChannel[1].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   EgrDbSetup.EgrDbChannel[1].EgressDioOffset = 0;
   EgrDbSetup.bEnableChannel[2] = TRUE; //Enable Egress DB channel 2
   EgrDbSetup.EgrDbChannel[2].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_2; //Set DB RAM base address for channel 2
   EgrDbSetup.EgrDbChannel[2].DataSwap = CSL_AIF2_DB_BYTE_SWAP; //For UL
   EgrDbSetup.EgrDbChannel[2].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   EgrDbSetup.EgrDbChannel[2].EgressDioOffset = 0;
   EgrDbSetup.bEnableChannel[124] = TRUE; //Enable Egress DB channel 124
   EgrDbSetup.EgrDbChannel[124].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_2 + 4; //Set DB RAM base address for channel 2
   EgrDbSetup.EgrDbChannel[124].DataSwap = CSL_AIF2_DB_NO_SWAP; //No swap
   EgrDbSetup.EgrDbChannel[124].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
   EgrDbSetup.EgrDbChannel[124].EgressDioOffset = 0;
   
   //AD Common and DIO setup
   AdCommonSetup.IngrGlobalEnable = TRUE;
   AdCommonSetup.EgrGlobalEnable = TRUE;
   AdCommonSetup.IngrGlobalDioEnable = TRUE;
   AdCommonSetup.EgrGlobalDioEnable = TRUE;
   AdCommonSetup.FailMode = CSL_AIF2_AD_DROP;//drop fail packet
   AdCommonSetup.IngrPriority = CSL_AIF2_AD_DIO_PRI;
   AdCommonSetup.EgrPriority = CSL_AIF2_AD_AXC_PRI;
   AdCommonSetup.Tx_QueNum = AIF2_BASE_TX_QUE_NUM;//base egress queue number setup to 512
   
   AdDioSetup.IngrDioEngineEnable[0] = TRUE;//Enable DIO Engine
   AdDioSetup.IngrDioEngine[0].BcnTableSelect = CSL_AIF2_AD_DIO_BCN_TABLE_0;
   AdDioSetup.IngrDioEngine[0].NumQuadWord = CSL_AIF2_AD_2QUAD;//Use 2 QW per channel
   AdDioSetup.IngrDioEngine[0].NumAxC = 2;//Using 3 AxC.(n-1)
   AdDioSetup.IngrDioEngine[0].bEnDmaChannel = TRUE; //Enable Dma channel
   AdDioSetup.IngrDioEngine[0].DmaNumBlock = 3;//4 block wrap value (n-1) 
   AdDioSetup.IngrDioEngine[0].DmaBurstLen = CSL_AIF2_AD_4QUAD;//4 max QW burst per one transfer
   AdDioSetup.IngrDioEngine[0].DmaBaseAddr = (Uint32)&dio_result[0];//DMA destination base address (use high 28 bits)
   AdDioSetup.IngrDioEngine[0].DmaBurstAddrStride = 4;//DMA burst stride to 4 (wrap1)
   AdDioSetup.IngrDioEngine[0].DmaBlockAddrStride = 6;//DMA block stride to 6 (wrap2)
   AdDioSetup.IngrDioEngine[0].DBCN[0] = 0; //set ingress table DBCN for channel 0
   AdDioSetup.IngrDioEngine[0].DBCN[1] = 1; //set ingress table DBCN for channel 1
   AdDioSetup.IngrDioEngine[0].DBCN[2] = 2; //set ingress table DBCN for channel 2

   AdDioSetup.EgrDioEngineEnable[0] = TRUE;//Enable DIO Engine
   AdDioSetup.EgrDioEngine[0].BcnTableSelect = CSL_AIF2_AD_DIO_BCN_TABLE_0;
   AdDioSetup.EgrDioEngine[0].NumQuadWord = CSL_AIF2_AD_2QUAD;//Use 2 QW per channel
   AdDioSetup.EgrDioEngine[0].NumAxC = 2;//Using 3 AxC.(n-1)
   AdDioSetup.EgrDioEngine[0].bEnDmaChannel = TRUE; //Enable Dma channel
   AdDioSetup.EgrDioEngine[0].bEnEgressRsaFormat = TRUE; //Enable UL RSA data format (2QW/AxC)
   AdDioSetup.EgrDioEngine[0].DmaNumBlock = 3;//4 block wrap value (n-1) 
   AdDioSetup.EgrDioEngine[0].DmaBurstLen = CSL_AIF2_AD_4QUAD;//4 max QW burst per one transfer
   AdDioSetup.EgrDioEngine[0].DmaBaseAddr = (Uint32)&dio_data[0];//DMA source base address (use high 28 bits)
   AdDioSetup.EgrDioEngine[0].DmaBurstAddrStride = 4;//DMA burst stride to 4 (wrap1)
   AdDioSetup.EgrDioEngine[0].DmaBlockAddrStride = 6;//DMA block stride to 6 (wrap2)
   AdDioSetup.EgrDioEngine[0].DBCN[0] = 0; //set egress table DBCN for channel 0
   AdDioSetup.EgrDioEngine[0].DBCN[1] = 1; //set egress table DBCN for channel 1
   AdDioSetup.EgrDioEngine[0].DBCN[2] = 2; //set egress table DBCN for channel 2

   //AT Common setup
   //AtCommonSetup.PhySyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Phy timer trigger
   //AtCommonSetup.RadSyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Rad timer trigger
   AtCommonSetup.PhySyncSel = CSL_AIF2_CHIP_INPUT_SYNC;
   AtCommonSetup.RadSyncSel = CSL_AIF2_PHYT_CMP_SYNC;
   AtCommonSetup.SyncMode = CSL_AIF2_NON_RP1_MODE;
   AtCommonSetup.AutoResyncMode = CSL_AIF2_NO_AUTO_RESYNC_MODE;
   AtCommonSetup.CrcMode = CSL_AIF2_AT_CRC_DONT_USE;//Do not use RP1 CRC in this test
   
   AtCommonSetup.AtInit.pPhyTimerInit = &PhyTimerInit;
   AtCommonSetup.AtInit.pRadTimerInit = &RadTimerInit;
   AtCommonSetup.AtInit.pUlRadTimerInit = &UlRadTimerInit;
   AtCommonSetup.WcdmaDivTC = 63; //64 is default divide value for WCDMA CPRI
   PhyTimerInit.ClockNum = 0;
   PhyTimerInit.FrameLsbNum = 0;
   PhyTimerInit.FrameMsbNum = 0;
   RadTimerInit.ClockNum = 0;
   RadTimerInit.SymbolNum = 0;
   RadTimerInit.FrameLsbNum = 0;
   RadTimerInit.FrameMsbNum = 0;
   UlRadTimerInit.ClockNum = 160530;// 163840 - 3310(Ingress first DIO DMA offset(1262) + 32 chip time)
   UlRadTimerInit.SymbolNum = 14;
   UlRadTimerInit.FrameLsbNum = 0;
   UlRadTimerInit.FrameMsbNum = 0;
   AtCommonSetup.AtTerminalCount.pPhyTimerTc = &PhyTimerTc;
   AtCommonSetup.AtTerminalCount.pRadTimerTc = &RadTimerTc;
   PhyTimerTc.FrameLsbNum = FRAME_COUNT_TC_PHY_TIMER;//set phy Frame TC to 4095
   PhyTimerTc.ClockNum = CLOCK_COUNT_TC_PHY_TIMER_CPRI; //set phy clock TC to 2456799
   RadTimerTc.FrameLsbNum = FRAME_COUNT_TC_WCDMA_FDD;//set WCDMA Frame TC to 4095
   RadTimerTc.SymbolNum = SLOT_COUNT_TC_WCDMA_FDD; //set WCDMA Slot TC to 14
   AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = CLOCK_COUNT_TC_WCDMA_FDD_CPRI;
   
   //AT Event setup for test debug purpose (Event 0)
   AtEventSetup.AtRadEvent[0].EventSelect = CSL_AIF2_EVENT_0;//Select Event 0 just for this test program
   AtEventSetup.AtRadEvent[0].EventOffset = 0; //fine offset could be tuned. main offset is already applied to ulradt clock num init value.
   AtEventSetup.AtRadEvent[0].EvtStrobeSel = CSL_AIF2_ULRADT_FRAME; 
   AtEventSetup.AtRadEvent[0].EventModulo = 2457600; // CPRI frame size
   AtEventSetup.AtRadEvent[0].EventMaskLsb = 0xFFFFFFFF; //set all mask to 1's for WCDMA FDD
   AtEventSetup.AtRadEvent[0].EventMaskMsb = 0xFFFFFFFF; //set all mask to 1's for WCDMA FDD
   AtEventSetup.bEnableRadEvent[0] = TRUE;//Enable Event

    //AT Event setup to generate 32 chip trigger for RAC_B (Event 10)
   AtEventSetup.AtRadEvent[10].EventSelect = CSL_AIF2_EVENT_10;
   AtEventSetup.AtRadEvent[10].EventOffset = 0; 
   AtEventSetup.AtRadEvent[10].EvtStrobeSel = CSL_AIF2_ULRADT_FRAME; 
   AtEventSetup.AtRadEvent[10].EventModulo = 2047; //set Modulus count for event 1 (WCDMA 32 chip time)
   AtEventSetup.AtRadEvent[10].EventMaskLsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD
   AtEventSetup.AtRadEvent[10].EventMaskMsb = 0xFFFFFFFF; //set all mask to for WCDMA FDD
   AtEventSetup.bEnableRadEvent[10] = TRUE;//Enable Event
   
   //AT Event setup (In DIO 8 chip Event)
   AtEventSetup.AtIngrDioEvent[0].EventSelect = CSL_AIF2_IN_DIO_EVENT_0;//Select In DIO Event 0
   AtEventSetup.AtIngrDioEvent[0].EventOffset = 0;
   AtEventSetup.AtIngrDioEvent[0].EvtStrobeSel = CSL_AIF2_RADT_FRAME; 
   AtEventSetup.AtIngrDioEvent[0].EventModulo = 511; //set Modulus count for In DIO event 0 (WCDMA 8 chip time)
   AtEventSetup.AtIngrDioEvent[0].DioFrameEventOffset = 1122;//Pi Max(420) + 8 WCDMA chip time(512) + PD delay and fuzzy factors(190)
   AtEventSetup.AtIngrDioEvent[0].DioFrameStrobeSel = CSL_AIF2_RADT_FRAME; //frame event strobe selection
   AtEventSetup.bEnableIngrDioEvent[0] = TRUE;//Enable In DIO Event 0 
   
   //AT Event setup (E DIO 8 chip Event)
   AtEventSetup.AtEgrDioEvent[0].EventSelect = CSL_AIF2_E_DIO_EVENT_0;//Select E DIO Event 0
   AtEventSetup.AtEgrDioEvent[0].EventOffset = 0;
   AtEventSetup.AtEgrDioEvent[0].EvtStrobeSel = CSL_AIF2_RADT_FRAME; 
   AtEventSetup.AtEgrDioEvent[0].EventModulo = 511; //set Modulus count for E DIO event 0 (WCDMA 8 chip time)
   AtEventSetup.AtEgrDioEvent[0].DioFrameEventOffset = 0;//no frame event offset for Egress
   AtEventSetup.AtEgrDioEvent[0].DioFrameStrobeSel = CSL_AIF2_RADT_FRAME; //frame event strobe selection
   AtEventSetup.bEnableEgrDioEvent[0] = TRUE;//Enable E DIO Event 0 
   
   /****** Do AIF2 HW setup (set all MMRs above) **********************************************************************/
   CSL_aif2HwSetup(hAif2, &aif2Setup);
   
   ctrlArg = TRUE;
   hAif2->arg_link = CSL_AIF2_LINK_0;
   
   //Enable Serdes loopback for link 0
   //CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg);
   
   // Enable Tx/Rx of link 0
   CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
   CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);
   for(i=0; i<100; i++)asm (" NOP 9 ");//delay for aif2 MMR configuration
   
   //AT Arm timer
   CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_ARM_TIMER, (void *)&ctrlArg);
   
   //Trigger the SW debug frame sync
   //CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DEBUG_SYNC, (void *)&ctrlArg);
   //Start_timer0();
}

void main(void)
{
	
    Uint32  idx, idx2,axc =0;
    Uint16  testpass;
    
    printf("Beginning AIF2 WCDMA CPRI DIO test for RAC:\n\n");
    for(idx=0;idx<10000;idx++)asm (" NOP 9 ");//insert time delay for printf operation
    
    enable_module(aif_pdctl, aif_mdctl);//Enable AIF2 module power
    
    int4_result = 0;
    
    Intc_config();
    
    memset(dio_result, 0xFF, 384);
    
    //bit 31 ~ 24 : Symbol number bit 23~ 16 : AXC number bit15 ~ 0 :sample count
    for(idx =0; idx < 4; idx++){
       for (idx2 = 0; idx2 < 24; idx2 ++) {
	   	dio_data[(24*idx) + idx2] = idx2;
		dio_data[(24*idx) + idx2] |= (axc/8) << 16; axc++;
		dio_data[(24*idx) + idx2] |= idx << 24;
    }
	axc = 0;
    }
    
    MNavigator_config();
      
    Aif2_Dio_Cpri_Rac_config(); //Aif2 configuration for DIO RAC test

    /*****************************************************************
    * Enable AIF and wait for completion. */
    while(1)
    {
        asm (" NOP 9 ");
        asm (" NOP 9 ");
        if(int4_result == 3)// Wait two CPRI frame time 
        {
            //AT disable all events and halt timer
            ctrlArg = TRUE;
	    CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS, (void *)&ctrlArg);
            CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_HALT_TIMER, (void *)&ctrlArg);
	     ctrlArg = FALSE;//disable AD DIO and Rx, Tx Link
	     CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_DIO_GLOBAL, (void *)&ctrlArg);
            CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_DIO_GLOBAL, (void *)&ctrlArg);
	     CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
            CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);     
            // Disable  pkt dma channel 128
            enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 128, 0);//disable Tx channel 128
            enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, 128, 0);//disable Rx channel 128
            CSL_aif2Reset(hAif2);//reset all aif2 modules 
            break;
        }
    }

    /********************************************************************
    * Compare the DIO data and Control data in the destination buffers. */
    testpass = 0;
	/* Compare the DIO loopback data */
    testpass |= memcmp(&dio_data[0], &dio_result[0], 384);
   
    if (testpass == 0)
      printf(" DIO CPRI Loopback Data for WCDMA: PASS\n");
    else
      printf(" DIO CPRI Loopback Data for WCDMA: FAIL\n");
      
    testpass = 0;
	/* Compare the CPRI control data */
    testpass |= memcmp(&mono_region[12], &mono_region[16*720+12], 704);
   
    if (testpass == 0)
      printf(" CPRI Control Word(FastC&M) for WCDMA: PASS\n");
    else
      printf(" CPRI Control Word(FastC&M) for WCDMA: FAIL\n");

    printf("\nEnding AIF2 WCDMA CPRI DIO tests for RAC\n");
    
}