Problems about transferring data from C6678_A to C6678_B through hyperlink interface

Nuoxi Lin

Hi everyone,

I have a board on which there are two C6678 DSPs. The hyperlink interfaces of the two DSPs are connected directly.

I want to transfer data from C6678_A to C6678_B through hyperlink interface. I found a project named

hyplnk_exampleProject, which located at C:\ ti \pdk_C6678_1_0_0_17 \packages \ti \drv \exampleProjects\hyplnk_exampleProject.

In hyplnkExample.c, there are expalanations which says:

The synchronized token exchange requires the same SW on each endpoint.The asynchronous block transfers don't require any SW runing on the other endpoint,

however both sides can optimally run the test at the same time.

I selected asynchronous block transfers using CPU. But when I ran the project in C6678_A only ,the console window showed,"Waiting for other side to come up(n)"

Did I make some mistake? If I have done wrong,then how to implement data transfers between two DSPs through hyperlink interface?Please help me.

I am looking forward to your reply.

Best Regards,

Nuoxi

over 13 years ago

0 Chad Courtney over 13 years ago

TI__Mastermind 30825 points

The basic configuration, such as enabling the power domain and performing the SerDes configuration of the HyperLink not running the SW would still be required.

Best Regards,
Chad

0 Nuoxi Lin over 13 years ago in reply to Chad Courtney

Intellectual 650 points

Hello Chad,

If I ran the project in two DSPs simutaneously, then there are not any problem. But i want to set C6678_A as local endpoint and C6678_B as remote endpoint.

I have enabled the power domain and performed the SerDes configuration of the hyperlink for C6678_B. Then I run the hyplnkExampleProject in C6678_A, but the

console window still shows"Waiting the other side to come up( n)". Could you give me more suggestions? What configurations should be done for C6678_B except for

enablingthe power domain and performing the SerDes configuration of hyperlink?

Thanks in advance.

Best Regards,

Nuoxi

0 Nuoxi Lin over 13 years ago in reply to Chad Courtney

Intellectual 650 points

Hi Chad,

Thanks for your reply. Now I have implemented data transfers between two DSPs. But I have another questions.

If I changed the link speed to 4*12.5Gbps for hyperlinks of two DSPs,then the project in C6678_A didn't work well.

When I ran C6678_A,the console window showed the following messages:

. ......................some basic information.....................

=============begin registers before initialization====================

Revision register contents:

Raw = 0x4e901900

Status register contents:

Raw = 0x00002004;

Link status register contents:

Raw = 0x00000000;

Control register contents:

Raw = 0x00000001;

Control register contents:

Raw = 0x00000000;

=================end registers before initialization===================

Fatal error detected

Local fatal isr status.rError = 1

Could you tell me why this kind of error appears ? The user Guide for hyperlink indicates that it supports 12.5Gbps for each lane.

I am looking forward to your reply.Thanks in advance.

Best Regards,

Nuoxi

0 Chad Courtney over 13 years ago in reply to Nuoxi Lin

TI__Mastermind 30825 points

Please see the Errata Advisory 21, only 40GBaud operation is currently being supported do to a bug.

Best Regards,

Chad

0 Albert Bae over 13 years ago in reply to Chad Courtney

TI__Expert 4740 points

Hi Nuoxi,

For DSP to DSP communication with hyperlink, the SERDES configuration timing is very important. you'd better at least power on SERDES and enable it before running your application when local, remote mode is used.

About link speed, Chad already explained above why we can support 40 GBaud. if you are using external prototype cable between Hyperlinks (not on board connection), the total BW should be less than 25 GBaud to make it work without error.

Regards,

Albert

0 Nuoxi Lin over 13 years ago in reply to Albert Bae

Intellectual 650 points

Hi Albert,

Thanks for your reply and I am very sorry for the dalay. For the link speed of 4*6.5Gbps, I have tested the data transmission rate between two DSPs through hyperlink

is only 150MBytes/s . I think the rate is too low. Could you tell me the reasonable data rate ? Thank you.

Best Regards,

Nuoxi

0 Albert Bae over 13 years ago in reply to Nuoxi Lin

TI__Expert 4740 points

Nuoxi,

If everything is OK, your perpormance should be better than that.

check your SERDES configuration if link rate and lane mode setup is correct. also check your ref clock is set correct.

if you are using external cable to connect each Hyperlink and it has very high level of noise, the performance will be lower than you expected.

If you are using Hyperlink LLD, you can easily change the link speed and other option by only modifying one of the header file in the LLD.

if you used CPPI instead of EDMA, the performance could be lower than your expectation.

Please refer to our example code for hyperlink setup. if you can not find any problem on it, the problem must come from the physical connection or your application.

Regards,

Albert

0 Nuoxi Lin over 13 years ago in reply to Albert Bae

Intellectual 650 points

Hi Albert,

Both the link rate and lane mode setup are correct. And the hyperlink interface of two DSPs are connected directly.

With your instruction, I found a possible problem which may result in the low rate. In your example code,which locates at

pdk_C6678_1_0_0_17\ packages \ti\ drv\ exampleProjects\ hyplink_exampleProject\ hyplnkExample.c, there is a function

called hyplnlExampleCPUBlockXfer(). In this function, the contents of the remote buffer are set to some certain value directly.

I want to use EDMA function instead, which will increase the data rate. But when i use EDMA,the data can't be written into the

remote buffer. The remote buffer are set to zeros.

I have verified that the EDMA function is correct. And the hyperlink user guide says it supports EDMA. Then why this happened?

I am looking forward to your reply. Thank you.

Best Regards,

Nuoxi

0 Albert Bae over 13 years ago in reply to Nuoxi Lin

TI__Expert 4740 points

Nuoxi,

I'm not the designer of Hyperlink LLD, so I have no idea about what that API is doing.

Anyway, I attached my own EDMA access style example code. you may compare line by line with your configuration.

Hope this could help to you.

Regards,

Albert

Fullscreen 4403.hyperlink_functions.c Download

/******************************************************************************
*              	 File Description
*	        	 ================
*
*   File Name		:	hyperlink_functions.c
*
*   Description		:	Common functions for MCM(Hyperlink).
*
*******************************************************************************/
#include <stdio.h>
#include <ti/csl/cslr.h>
#include <ti/csl/cslr_tpcc.h>
#include <ti/csl/csl_edma3.h>
#include <ti/csl/csl_edma3Aux.h>
#include <ti/csl/csl_cache.h>
#include "Hyperlink_config.h"

#define btcfg_cfg_base  0x02620000 //Chip level registers base

CSL_Edma3Handle hModule, hModule1, hModule2;
CSL_Edma3ParamHandle paramHandle0;
CSL_Edma3ParamHandle paramHandle1;

CSL_Edma3ChannelAttr  chParam;
CSL_Edma3ChannelObj  ChObj0;
CSL_Edma3ChannelHandle  hChannel0;
CSL_Edma3ChannelObj  ChObj1;
CSL_Edma3ChannelHandle  hChannel1;
CSL_Edma3HwDmaChannelSetup chSetup;
CSL_Edma3ParamSetup paramSetup; 
CSL_Edma3Obj  moduleObj;
CSL_Edma3CmdIntr regionIntr,regionIpr;
CSL_Status EdmaStat, handleStatus;

static int mcm_reg_wr(volatile int *reg, int val)
{
	*reg = val;
	return PASS;
}

static int mcm_reg_rd(volatile int *reg)
{
	int val;
	 val = *reg;
	 return val;
}

void write_local_reg (unsigned int offset, unsigned int bit_position)
{
    unsigned int wr_val;
    unsigned int i = 0x1;
    
	wr_val = ((mcm_reg_rd((volatile int *)(CSL_MCM_CONFIG_REGS + offset))) | (i << bit_position));

    mcm_reg_wr(((volatile int *)(CSL_MCM_CONFIG_REGS + offset)),wr_val);
}


void Configure_vUSR_SerDes( void )
{
  int val;
  
  //unlock device control configuration area to setup Hyperlink SERDES (TI internal registers)
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+0x38),0x83e70b13); //KICK0 key setup
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+0x3c),0x95a4f1e0); //KICK1 key setup

  /*** Hyper bridge SERDES configuration (User may use SRIO SERDES register map for this)*****/ 
  /* Configure SERDES PLL 
  CFGPLL[0] ENPLL = 0 (VUSR overrides this value)
  CFGPLL[8:1] MPY = 40(10x)for 312.50MHz input clock, 80(20x)for 156.25MHz, 50(12.5x) for 250MHz to get max speed 3.125GHz
  CFGPLL[9] VRANGE = 1 for full rate and half rate. 0 for quad rate and eighth rate  
  CFGPLL[10] SLEEPPLL = 0
  CFGPLL[12:11] LOOP BANDWIDTH = 0   CFGPLL[14:13] sCLKBYP = 00 no Bypass */
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGPLL), 0x250);

  /* Configure CFGRX
  CFGRX [0] ENRX = 1 Don't care (Overwritten automatically by VUSR)  CFGRX [3:1] BUSWIDTH = 2
  CFGRX [5:4] RATE = 0 full rate (4 bit per clock) 3.125GHz * 4 = 12.5Gbps max speed per lane  
  CFGRX [6] INVPAIR = 0  CFGRX [9:7] TERM =  1 (1 for AC couple and 6 for DC couple)
  CFGRX [11:10] ALIGN = 01 Don't care (Overwritten by VUSR in run time)  
  CFGRX [14:12] LOS = 100 (vUSR automatically sets to 0 for loopback. User must set to 4 for non-loopack)
  CFGRX [17:15] CDR = 101      CFGRX [20:18] EQ = 001 
  CFGRX [21] EQHLD = 0     CFGRX [22] ENOC = 1   
  CFGRX [24:23] LOOPBACK = 00 Automatically configured by vUSR HW
  CFGRX [27:25] TESTPATTERN = 000  */
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGRX0), 0x0046C485);
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGRX1), 0x0046C485);
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGRX2), 0x0046C485);
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGRX3), 0x0046C485);
  
  /* Configure CFGTX 
  CFGTX [0] ENTX = 1 Don't care (Overwritten automatically by VUSR)   CFGTX [3:1] BUSWIDTH = 2
  CFGTX [5:4] RATE = 0 full rate (4 bit per clock) 3.125GHz * 4 = 12.5Gbps max speed per lane  
  CFGTX [6] INVPAIR = 0  
  CFGTX [10:7] SWING = 1110b  7 for short trace length and 15 for long trace length
  CFGTX [13:11] TWPRE = 001b Precursor Tap weight. (-2.5%)
  CFGTX [18:14] TWPST1 = 18(10010b) Adjacent Post Cursor Tap Weight 
  If trace length is 4� or less, use 23 (-10%). If trace length is between 4� and 10�, use 27 (-27.5%).
  CFGTX [19] FIRUPT = 1   Transmitter pre and post cursor FIR filter update    
  CFGTX [20] MSYNC = 1 (vUSR will automatically set this value)     
  CFGTX [22:21] LOOPBACK = 00 (vUSR will automatically set this field)
  CFGTX [25:23] TESTPATTERN = 000  */
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGTX0), 0x001C8F05 );
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGTX1), 0x001C8F05 );
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGTX2), 0x001C8F05 );
  mcm_reg_wr((volatile int *)(btcfg_cfg_base+VUSR_SERDES_CFGTX3), 0x001C8F05 );
  
  //check for PLL lock
  val =  mcm_reg_rd((volatile int *)(btcfg_cfg_base+STS_VUSR));
  while(!(val & 1))
  {
  	val =  mcm_reg_rd((volatile int *)(btcfg_cfg_base+STS_VUSR));
  }
  	
}


void vUSR_InternalLoopBackEnable()
{
  int val;
  write_local_reg(4, 2);
  write_local_reg(4, 1);

  val = mcm_reg_rd((volatile int *)CSL_MCM_CR);
  val = val & 0xFFFFFFFB;
  mcm_reg_wr(((volatile int *)CSL_MCM_CR), val);

}

void vUSR_NonLoopBack_LinkOnWait()
{
  int val, retryCount = 0;
  uint64_t wait_start, time_waited;
  
  /* Wait for other peripheral to come up */
  wait_start = DSP_ReadTime64();
  do {
    val = mcm_reg_rd((volatile int *)CSL_MCM_SR);
    val = val & 0x00003001;
  
    time_waited = (DSP_ReadTime64() - wait_start);
    if ((! time_waited) || (time_waited > 1000000000)) {

    printf ("Waiting for other side to come up (%8d)\n", retryCount);
    wait_start = DSP_ReadTime64();
    retryCount++;
    }
  } while (val != 0x1);
	
}

void vUSR_ModuleReset()
{
  int val,i;
  write_local_reg(4, 2);
  write_local_reg(4, 0);//reset

  for(i=0;i<100;i++)asm(" NOP 5 ");
  val = mcm_reg_rd((volatile int *)CSL_MCM_CR);
  val = val & 0xFFFFFFFA;
  mcm_reg_wr(((volatile int *)CSL_MCM_CR), val);
  
   volatile Uint32 *pi;
   // Empty queues (to avoid not working the 2nd time)... */
   for (pi = (volatile Uint32 *)0x02a20000; pi < (volatile Uint32 *)(0x02a20000 + 0x20000); pi += 4)
   {
      pi[2] = 0;
      pi[3] = 0;
   }
}


void CheckLinkStatus(void)
{
    while ((mcm_reg_rd((volatile int *)CSL_MCM_SR) & (0x1)) != 0x1);//check link enable
	
    while ((mcm_reg_rd((volatile int *)CSL_MCM_SR) & (0xF000)) != 0x0);//check serial halt and pll unlock
}	


void configure_address_mappings(Uint32 Txigmask, Uint32 rxsegsel, Uint32 RxBufAddr1, Uint32 RxBufAddr2)
{

	Uint32 rxAddrOffset1 = 0, rxAddrOffset2 = 0;
	Uint32 rxlen_val;
	
	rxAddrOffset1 = RxBufAddr1;
	rxAddrOffset2 = RxBufAddr2;
		
	mcm_reg_wr((volatile int *)CSL_MCM_TXADDOVLCTL, Txigmask);//configure Tx address overlay (PrivID = 0, Sec = 0)
	CheckLinkStatus();
	
    //Rx Address Selector Control (PrivID = 0, Sec = 0)
    if(rxsegsel == 0x1)rxlen_val = 16;
    else if(rxsegsel == 0x2)rxlen_val = 17;
    else if(rxsegsel == 0x3)rxlen_val = 18;
    else if(rxsegsel == 0x4)rxlen_val = 19;
    
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDSELCTL, rxsegsel);
	
    //Remote Rx Adress PrivID Index
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDPRVIDX, 0x0);

    //Remote Rx Adress PrivID Value Register
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDPRVVAL, 0x0);

    //Remote Rx Adress Segment Index Register for remote QM
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDSEGIDX, 0x0);
	  	
    //Rx Adress Segment Value Register for remote QM
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDSEGVAL, ((rxAddrOffset1 & 0xFFFF0000)+rxlen_val));
	 
	//Remote Rx Adress Segment Index Register for remote MSMC
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDSEGIDX, 0x2);
	  	
    //Rx Adress Segment Value Register for remote MSMC
	mcm_reg_wr((volatile int *)CSL_MCM_RXADDSEGVAL, ((rxAddrOffset2 & 0xFFFF0000)+rxlen_val));
	
}

void configure_remote_address_mappings(Uint32 Txigmask, Uint32 rxsegsel, Uint32 RxBufAddr1, Uint32 RxBufAddr2)
{

	Uint32 rxAddrOffset1 = 0, rxAddrOffset2 = 0;
	Uint32 rxlen_val;
	
	rxAddrOffset1 = RxBufAddr1;
	rxAddrOffset2 = RxBufAddr2;
		
	mcm_reg_wr((volatile int *)CSL_RMCM_TXADDOVLCTL, Txigmask);//configure Tx address overlay (PrivID = 0, Sec = 0)
	
    //Rx Address Selector Control (PrivID = 0, Sec = 0)
    if(rxsegsel == 0x1)rxlen_val = 16;
    else if(rxsegsel == 0x2)rxlen_val = 17;
    else if(rxsegsel == 0x3)rxlen_val = 18;
    else if(rxsegsel == 0x4)rxlen_val = 19;
    
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDSELCTL, rxsegsel);
	
    //Remote Rx Adress PrivID Index
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDPRVIDX, 0x0);

    //Remote Rx Adress PrivID Value Register
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDPRVVAL, 0x0);

    //Remote Rx Adress Segment Index Register for remote QM
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDSEGIDX, 0x0);
	  	
    //Rx Adress Segment Value Register for remote QM
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDSEGVAL, ((rxAddrOffset1 & 0xFFFF0000)+rxlen_val));
	 
	//Remote Rx Adress Segment Index Register for remote MSMC
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDSEGIDX, 0x2);
	  	
    //Rx Adress Segment Value Register for remote MSMC
	mcm_reg_wr((volatile int *)CSL_RMCM_RXADDSEGVAL, ((rxAddrOffset2 & 0xFFFF0000)+rxlen_val));
	
}


void configure_address_mappings_EDMA(Uint32 Txigmask, Uint32 rxadrsize1, Uint32 RxAddrOffset)
{

	Uint32 rxadroffset1 = 0x0;
	Uint32 rxregsel,rxlen_val;
	if(((Uint32)RxAddrOffset & 0xFFF00000) == 0x00800000) 
		rxadroffset1 = 0x10000000 + (Uint32)RxAddrOffset;//core 0
	else
		rxadroffset1 = RxAddrOffset;
		
	mcm_reg_wr((int *)CSL_MCM_TXADDOVLCTL, Txigmask);
	CheckLinkStatus();
    //Rx Address Selector Control
    if (rxadrsize1 < 0x1FFFF)
      {
      rxregsel = 0x1;
      rxlen_val = 16;
      }
    else if (rxadrsize1 < 0x3FFFF)
      {
      rxregsel = 0x2;
      rxlen_val = 17;
      }
    else if (rxadrsize1 < 0x7FFFF)
      {
      rxregsel = 0x3;
      rxlen_val = 18;
      }
    else if (rxadrsize1 < 0xFFFFF)
      {
      rxregsel = 0x4;
      rxlen_val = 19;
      }
	mcm_reg_wr((int *)CSL_RMCM_RXADDSELCTL, rxregsel);
	
  //Remote Rx Adress PrivID Index
	mcm_reg_wr((int *)CSL_RMCM_RXADDPRVIDX, 0x0);

  //Remote Rx Adress PrivID Value Register
	mcm_reg_wr((int *)CSL_RMCM_RXADDPRVVAL, 0x0);

  //Remote Rx Adress Segment Index Register
	mcm_reg_wr((int *)CSL_RMCM_RXADDSEGIDX, 0x0);
	  	
  //Rx Adress Segment Value Register
	mcm_reg_wr((int *)CSL_RMCM_RXADDSEGVAL, ((rxadroffset1 & 0xFFFFF000)+rxlen_val));
		
}

void trigger_edma_rd_channel()
{
	   	CSL_edma3HwChannelControl(hChannel0,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
}
void trigger_edma_wr_channel()
{
	CSL_edma3HwChannelControl(hChannel1,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
}


void vusr_edma_rd_setup_all_payload(Uint32 srcBuf, Uint32 dstBuf, Uint32 payload, Uint32 channel_num)
{
    // EDMA Module Initialization
	CSL_edma3Init(NULL);
 
 	// EDMA Module Open	
    hModule = CSL_edma3Open(&moduleObj,CSL_TPCC_0,NULL,&EdmaStat);

	chParam.regionNum  = CSL_EDMA3_REGION_GLOBAL;
	//chSetup.que        = CSL_EDMA3_QUE_0;
	chParam.chaNum     = channel_num;

    /* NySh Tx Channel */
	hChannel0 = CSL_edma3ChannelOpen(&ChObj0, CSL_TPCC_0, &chParam, &EdmaStat);
	chSetup.paramNum   = chParam.chaNum;
    CSL_edma3HwChannelSetupParam(hChannel0,chSetup.paramNum);
	paramHandle0            = CSL_edma3GetParamHandle(hChannel0,channel_num,&EdmaStat);

    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(payload*4,1);       		
	paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(4,4 );  
	paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);     		
	paramSetup.cCnt         = 1;
	paramSetup.option       = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,channel_num,CSL_EDMA3_TCC_NORMAL, \
	      CSL_EDMA3_FIFOWIDTH_NONE,FALSE,CSL_EDMA3_SYNC_AB,CSL_EDMA3_ADDRMODE_INCR,CSL_EDMA3_ADDRMODE_INCR);
		      
	paramSetup.srcAddr      = (Uint32)srcBuf;
	if( ((Uint32)dstBuf & 0xFFF00000) == 0x00800000) 
		paramSetup.dstAddr      = (Uint32)(0x10000000 + (Uint32)dstBuf);
	else
		paramSetup.dstAddr      = (Uint32)dstBuf;	
	paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);     

	CSL_edma3ParamSetup(paramHandle0,&paramSetup);
	CSL_edma3HwChannelControl(hChannel0,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
	trigger_edma_rd_channel();
}

void vusr_edma_wr_setup_all_payload(Uint32 srcBuf, Uint32 dstBuf, Uint32 payload, Uint32 channel_num)
{
    // EDMA Module Initialization
	CSL_edma3Init(NULL);
 
 	// EDMA Module Open	
    hModule = CSL_edma3Open(&moduleObj,CSL_TPCC_0,NULL,&EdmaStat);

	chParam.regionNum  = CSL_EDMA3_REGION_GLOBAL;
    //chSetup.que        = CSL_EDMA3_QUE_0;
	chParam.chaNum     = channel_num;

    /* NySh Tx Channel */
	hChannel1 = CSL_edma3ChannelOpen(&ChObj1, CSL_TPCC_0, &chParam, &EdmaStat);
	chSetup.paramNum   = chParam.chaNum; 
    CSL_edma3HwChannelSetupParam(hChannel1,chSetup.paramNum);
	paramHandle1            = CSL_edma3GetParamHandle(hChannel1,channel_num,&EdmaStat);

    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(payload*4,1);       		
	paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(4,4 );  
	paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);     		
	paramSetup.cCnt         = 1;
	paramSetup.option       = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,channel_num,CSL_EDMA3_TCC_NORMAL, \
	      CSL_EDMA3_FIFOWIDTH_NONE,FALSE,CSL_EDMA3_SYNC_AB,CSL_EDMA3_ADDRMODE_INCR,CSL_EDMA3_ADDRMODE_INCR);
	
	if( ((Uint32)srcBuf & 0xFFF00000) == 0x00800000)
		paramSetup.srcAddr      = (Uint32)(0x10000000 + (Uint32)srcBuf);
	else
		paramSetup.srcAddr      = (Uint32)srcBuf;

		paramSetup.dstAddr      = (Uint32)dstBuf;
	paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);     

	CSL_edma3ParamSetup(paramHandle1,&paramSetup);
	CSL_edma3HwChannelControl(hChannel1,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
	trigger_edma_wr_channel();
}

void verify_edma_complete(int ch_num)
{
    Uint32 val;
    regionIpr.region  = CSL_EDMA3_REGION_GLOBAL;
	regionIpr.intr    = 0;
	regionIpr.intrh   = 0;
	
	val = 1 << (ch_num);
	
	do{
		CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIpr);
	}while ((regionIpr.intr & val) != val);// channel 8 ~
}

0 Albert Bae over 13 years ago in reply to Albert Bae

TI__Expert 4740 points

Attached one more file

Fullscreen 3386.Hyperlink_EDMA_throughput_test.c Download

/****************************************************************************\
 *           Copyright (C) 2009 Texas Instruments Incorporated.             *
 *                           All Rights Reserved                            *
 *                                                                          *
 * GENERAL DISCLAIMER                                                       *
 * -------------------------------------------------------------------------*
 * All software and related documentation is provided "AS IS" and without   *
 * warranty or support of any kind and Texas Instruments expressly disclaims*
 * all other warranties, express or implied, including, but not limited to, *
 * the implied warranties of merchant ability and fitness for a particular   *
 * purpose.  Under no circumstances shall Texas Instruments be liable for   *
 * any incidental, special or consequential damages that result from the    *
 * use or inability to use the software or related documentation, even if   *
 * Texas Instruments has been advised of the liability.                     *
 ****************************************************************************
 *                                                                          *
 * Written by :                                                             *
 *            Albert Bae                                                    *
 *            Texas Instruments                                             *
 *            01 Feb, 2011                                                 *
 *                                                                          *
 ***************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h> 
#include <c6x.h>
#include <ti/csl/csl.h>
#include <ti/csl/csl_chip.h>
/* HyperLink CSL include */
#include "Hyperlink_config.h"
#include "psc_util.h"
   
#define PAYLOAD 8192
#pragma DATA_SECTION(srcBuf1,".gem0_data")
#pragma DATA_ALIGN(srcBuf1, 32)
Uint32 srcBuf1[PAYLOAD];
#pragma DATA_SECTION(dstBuf1,".gem0_data2")
#pragma DATA_ALIGN(dstBuf1, 32)
Uint32 dstBuf1[PAYLOAD] ;
#pragma DATA_ALIGN(dstBuf2, 32)
Uint32 dstBuf2[PAYLOAD];

#define iLoopModeOn //comment this line for non loopback mode

Uint32 profileWr[7];
Uint32 aetCountWr[7], aetCountRd[7];

CSL_Uint64 profileWrStart = 0;
CSL_Uint64 profileWrStop = 0;

extern CSL_Uint64 CSL_tscRead();
extern CSL_Uint64 CSL_tscEnable();
extern void memset();

void Hyperlink_config(void)
{
    /************ Initialize Hyperlink ************************************************/ 
    
	/* Start Hyperlink module Serdes */
    Configure_vUSR_SerDes();
    
    /*	Enable all four lanes */
    *((int *)CSL_MCM_LPMC) |= 0x4;//0x4 quad lane, 0x2 single lane
    //*((int *)CSL_MCM_LPMC) &= 0xFFFFFFA;//single lane
    *((int *)CSL_MCM_LPMC) &= 0xFFFFFFC;// quad lane
    
#ifdef iLoopModeOn
    vUSR_InternalLoopBackEnable(); //internal loopback mode on
#else
    vUSR_NonLoopBack_LinkOnWait(); //wait until the vUSR in other DSP is turned on
#endif
}

void Setup_Aet(Uint32 channelNum,Uint32 tccNum)
{
	// Setup EDMA registers
	AET_CMD = 0x1;
	AET_CTL = CSL_FMKT(EDMA3CC_AETCTL_EN,ENABLE)| \
		CSL_FMK(EDMA3CC_AETCTL_ENDINT,tccNum)| \
		CSL_FMKT(EDMA3CC_AETCTL_TYPE,DMA)| \
		CSL_FMK(EDMA3CC_AETCTL_STRTEVT,channelNum);

	// Assign the event id depending on the GEM
	// CPU/2 EDMA 0 AET EVT is mapped to 37 of CPINTC 0 
	GEM_AEG_MUX0 = EDMACC0_AETEVT_GEM;
		
	// Setup AEG Registers in Interrupt Controller
	AET_claim();
	AET_countEvents(2, 
                    CSL_FMKT(AET_AE_ENA_AEGEVT0,SET),
                    0);
	AET_enable();                    
}	

Uint32 Retrieve_Aet()
{
	return (-(AET_counter0Read()));
}

void Hyperlink_Close(void)
{
   vUSR_ModuleReset();//reset vUSR module
}

void Test_result(void){
	Uint32 Tput = 0, i, packet_len;
	
    printf(" Test Result) VUSR Packet Data Send/Recv via EDMA: PASS\n");
    
    for(i=0; i<4; i++){
       switch(i)
       {
		  case 0:packet_len = 1024; break;
		  case 1:packet_len = 2048; break;
		  case 2:packet_len = 4096; break;
		  case 3:packet_len = 8192; break;
       }
       Tput = (packet_len*4*8)/aetCountWr[i];
       printf(" Packet Length: %d Byte. Data throughput is %d Gbps \n",packet_len,Tput);
    }
    
    printf("Ending Hyperlink Write/Read access and Throughput test via EDMA\n");
}

Uint32 verify_data(Uint32 *srcBuf, Uint32 *dstBuf, Uint32 payload)
{
	int i;
	
	for (i=0;i<payload;i++)
	{
		if (srcBuf[i] != dstBuf[i])
			return FAIL;
	}
	return PASS;
}

void corrupt_VUSR_data(int count)
{
	int i;
	for(i=0;i<count;i++)
	(*(int *)(0x40000000+i*4)) = 0;
}

void main(void)
{
    Uint32 result = FAIL;
	Uint32 i, payload;
	
    printf("\nBeginning Hyperlink Write/Read access and Throughput test via EDMA:\n");
    
    enable_module(mcm_pdctl, mcm_mdctl);//Enable Hyperlink module power
    
    CSL_tscEnable(); /* Enable the TSC */
    
    memset(dstBuf1, 0xFF, sizeof(dstBuf1));
    memset(dstBuf2, 0xFF, sizeof(dstBuf2));
    
    for(i=0; i<8192; i++)
    srcBuf1[i] = (Uint32)i; 
    
    Hyperlink_config();//hyperlink configuration for Cppi mode
    
    /* Write Testcase */
	for(i=0;i<4;i++)
	{	
    	
		/*Write Operation */    
		configure_address_mappings_EDMA(0xD, 0x7000,(Uint32)dstBuf1);

        // Setup AET related registers
		Setup_Aet(MCM_EDMA_WR_CHANNEL+i,MCM_EDMA_WR_CHANNEL+i); // Start from Channel 0 and end to Interrupt on TCC 0
    
    	switch(i)
    	{
			case 0:payload = 1024; break;
			case 1:payload = 2048; break;
			case 2:payload = 4096; break;
			case 3:payload = 8192; break;
    	}
		vusr_edma_wr_setup_all_payload((Uint32)srcBuf1, CSL_MCM_DATA, payload,MCM_EDMA_WR_CHANNEL+i);
        profileWrStart = CSL_tscRead();
        
		verify_edma_complete(MCM_EDMA_WR_CHANNEL+i);
		while(dstBuf1[payload-1] != srcBuf1[payload-1]);
		profileWrStop = CSL_tscRead();
		profileWr[i] =  profileWrStop - profileWrStart;
		
		aetCountWr[i] = Retrieve_Aet();	
		
		result = verify_data(srcBuf1, dstBuf1, payload);	
		if(result == FAIL){
			printf("Write Test data verification Failed. Test Halted\n");
			return;
		}
		corrupt_VUSR_data(payload);		
	}
    /*Read Testcase with loopback*/
	for(i=0;i<4;i++)
	{	
		/*Read Operation */    
		configure_address_mappings_EDMA(0xD, 0x2000,(Uint32)srcBuf1);

    	// Setup AET related registers
		Setup_Aet(MCM_EDMA_RD_CHANNEL+i,MCM_EDMA_RD_CHANNEL+i); // Start from Channel 0 and end to Interrupt on TCC 0
    
    	switch(i)
    	{
			case 0:payload = 1024; break;
			case 1:payload = 2048; break;
			case 2:payload = 4096; break;
			case 3:payload = 8192; break;
    	}
		vusr_edma_rd_setup_all_payload(CSL_MCM_DATA, (Uint32)dstBuf2, payload,MCM_EDMA_RD_CHANNEL+i);
	 
		verify_edma_complete(MCM_EDMA_RD_CHANNEL+i);
		aetCountRd[i] = Retrieve_Aet();	
		
		result = verify_data(srcBuf1, dstBuf2, payload);	
		if(result == FAIL){
			printf("Read Test data verification Failed. Test Halted\n");
			return;
		}
		//corrupt_VUSR_data(payload);
	}		
    
    Test_result(); //compare Tx, Rx data
    
    Hyperlink_Close();
        
}

0 Nuoxi Lin over 13 years ago in reply to Albert Bae

Intellectual 650 points

Hi Albert,

Thank you very much for your help. I will try again.

Best Regards,

Nuoxi

Processors

Processors forum

Problems about transferring data from C6678_A to C6678_B through hyperlink interface