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GMII Interface Description Clarification

Paul Joseph
Expert 2795 points

Is this a mistake in this document?

 Table 14-5. GMII Interface Signal Descriptions in GIG (1000Mbps) Mode

 The receive data pins are a collection of 8 data signals comprising 8 bits of

MRXD I data.MRXD0 is the least-significant bit (LSB).The signals are synchronized by

MRCLK and valid only when MRXDV is asserted.

 Seems that this should be 4 bits as with the MTXD.

 Also, I read the GMII does not work in this IC – is this correct?

  • 0
    TI__Guru 62945 points

    This Section of the TRM describes the Ethernet subsystem used in AM335x.  Table 14-1of the Unsupported Features sub-section describes Ethernet subsystem features which are not supported in AM335x.  GMII is one of the features not support.  

    The Ethernet MAC/Switch implemented in the AM335x device supports GMII mode, but the AM335x design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the remaining GMII signals.

    Regards,
    Paul