Generating interrupts on hyperlink recieve

Hi,

What kind of Data transfer method you are using? there are three options (QMSS, EDMA, CPU direct access)

If you use QMSS to transfer packet data to remote device, you can use QMSS accumulator interrupt on remote DSP and you don't need to use hyperlink interrupt in this case. Actually, this is simplest way to generate transfer complete interrupt. if you want to use this way, I can give you my example code about how to setup QMSS and accumulator.

However, if you want to use EDMA or CPU direct access for local side for data sending, your application needs to use Generate soft interrupt value register like you mentioned above. Unfortunately, I haven't used the register before and need to take a look to get correct usage of the register. it requires several days to me to confirm the fuctionality because it was only proven by our design team and our application level test didn't cover that.

Please let me know your choice and then we can go further steps.

Regards,

Albert

Albert,

Currently, I am using CPU direct access on the local side for data transfer.  If possible, I would like to stay with this (mostly because I have the transfer code in a working state that I hesitate to change). 

I would be happy to look at the example code you have for the QMSS accumulator interrupt, although I am not sure if this would be applicable for the application I am working on. 

So, overall, I would appreciate any investigation into the soft interrupts, and would also like to take a look at the example you have for the QMSS and accumulator. 

Sincerely,

Mark

Hi Mark,

I understood that our users guide looks cofusing about interrupt.  you may need to spend more time for reading the section several times to fully understand how to set interrupt. I'll only explain how to set Soft interrupt to remote device.

Generate Soft Interrupt register has ivector field and the interrupt will be issued when you put right vector number into the field. before you set this, you need to setup other registers. first one is Control Register [intlocal = 0, intenable = 1] and Interrupt Control Index and Value register pair should be configured. icidx field in the Interrupt Control Index Register is the same value to ivector in Generate Soft interrupt register. you can select which hardware or software Interrupt Control register will be used for the soft interrupt.  Interrupt Control Value register should be set correctly before using soft interrupt. especially, the bit field 27 'sien' field should be set and dnid, mps, vector field can be used to select the remote processor and network identifier. the vector field decides which bit of intterupt pending register to set in the remote device.

for all other additional information, you can get detail from UG or Hyperlink LLD.

I also attached my own example code for CPPI(QMSS) and EDMA test. hope that could help to you.

Regards,

Albert6622.Hyperlink_EVM_example_LE.zip 

Albert,

Thanks, that gives me some things to look into.  Any status on any example (or confirmation) of the software-generated interrupts working?

~ Mark

Mark,

unfortunately, we don't have that kind of example code and couldn't get a chance to run it on my side.

Maybe, I can do that later when all my urgent support and design related jobs can be closed.

Regards,

Albert

hi Albert, i notice you refered  " mps, vector field can be used to select the remote processor and network identifier" above,

My question is whether mps is to select which core to sevice the hyperlink interrupt ?

Now i need to interrupt a specified core in remote DSP as a notice after data transfer,  so i want to know

if i can interrupt the paticular core i want properly with a corresponding value in the mps field.

wish for your reply, Thanks!

Hi,

MPS is logical interrupt controller index used for Hyperlink configuration for both side. we can support max 8 index (0 ~ 7).

you can simply set index on Interrupt Pointer Index register (offset 0x68) and set real regsiter HW address by using Interrupt Pointer Value register(offset + 6C)

it depends on your decision what kind of interrupt controller (include DSP CPU interrupt controller) can be assigned for each index. 

Regards,

Albert 

"If the int2cfg for the remote device is set to 0x0, HyperLink sets the chip-level interrupt control register. The chip-level interrupt control register address is based on the MPS field carried in the interrupt packet. And th e vector field determines which bit of the chip-level interrupt control register is set."

this is from hyperlink user guide, and now suppose i have configured both send and receive sides properly , send side: intlocal = 0,  receive side: int2cfg = 0.

so i can send a interrupt packet to receive side , and int2cfg = 0 i rout this interrupt to write chip-level interrupt registers base on mps field, but what confuses me is how

mps  determine the chip-level interrupt register i write. in another word how can i know which chip-level interrupt register  i write ? cic0 channel map register? host interrupt enable register? event set  register?

I think you didn't correctly understand my previous comment. there is no fixed MPS number for each controller. it is just simple rising index and you can select real HW address for each index, so interrupt index number is matched with mps field in the interrupt control register. you can only differentiate the remote interrupt controller by the HW address, because each int controller has different memory mapped address in the DSP. the HW address means the interrupt set/pending regsiter address in each controller.

Albert

Hi , Albert, Thank you for you response.

You are right i think i havnt understood well in the hyperlink interrupt part.

Now what i want is to send interrupt packet form dsp A (6670)  to dsp B(6678), then  in dsp B a specified core services the interrupt.

This specified core is decided by software in dsp A.

you know there is only one interrupt output for hyperlink module, so it seems impossible to flexibly assign a paticular core in dsp B to service interrupt.

but above is the case when int2cfg is "1" in dsp B. When int2cfg  is "0" in dsp B,  the received interrupt packet goes to write chip level interrupt controller.

So, my question is which controller exactly the received interrupt packet writes .

it seems this written controller address is determined by mps and  interrupt pointer register value, but its not clear in my mind.

Could you explain this point to me .Thank you very much.

BTW,  Even today   i have done some small tests,  on dsp A side:

 intLocal  = 0;
int2cfg   = 0;
intCtrlIdx = 13;
SIEN = 1;
intEn = 1;
mps = 0;
vector = 1;
intPtrIdx = 0;
intPtr = 0x02600000 + 0x400; // 0x14
iVector = 13;

In dsp B, i simply set int2cfg = 0;

i checked many times in dsp B, and didnt find any memory is written by the interrupt packet.

but when i set int2cfg  = 1 in dsp B , the interrupt packet was forwarded well  to hyperlink output as expected. 

if you want to use two DSPs and transfer DSP_A interrupt to DSP_B, you can set intLocal to zero and the interrupt packet will be forwarded to remote DSP through Hyperlink. if the int2cfg bit is zero (like you did), it means the interrupt packet of DSP_A will be transferred to DSP_B any interrupt controller register area that was designated by your interrupt pointer register address setup. you set SIEN to one and that means you want to manually generate SW interrupt to set interrupt on remote DSP. it looks like you are still confused. 1462.Hyperlink_EVM_example_LE.zip

I attached my example project to show you a clear example how you can generate SW interrupt for Dual DSPs. this will help you to understand the basic concept.

Albert  

Hi Albert, Thank you for your reply.

let me tell you what i am working on this issue in detail.

I send interrupt packet from DSP_A to DSP_B,   in DSP_A i  set intlocal to zero, and also configured  all bout software interrupt correctly , and this worked well  because i

received   this very interrupt  packet in DSP_B ( when int2cfg = 1 in DSP_B). However actually  this is not what i want finnaly, then i go ahead.

When  i set int2cfg  to zero in DSP_B, i expected  this interrupt packet from DSP_A  to write chip level interrupt register in DSP_B, just as the user guide refered.

However  it turns out  nothing  written  in DSP_B.  Then i changed  "Interrupt pointer value"  in DSP_A to various address value , but still nothing is written in DSP_B.

e.g.   In DSP_A  i  set Interrupt pointer value to 0x2600400, which is address of cic0 channel map register, and mps is zero,  but still no channel map register is written .

And what's more ,  i even  output all the interrupt related memory area,  and still i saw this interrupt packet  wrote nothing in DSP_B.

THIS is what confuses me all the time.

SO, i want to know , 1.  are you sure  this interrupt packet  can write chip-level interrupt register  whose address is decided by Interrupt pointer register.

                                     2. If above is true, i must have wrongly understood somewhere about the interrupt packet transfer, i wish you point it out.

Wish your reply.

sincerely,

kaba.

Now I understood what you are trying to do. please try my suggestion below. you'd better set same configuration for both DSPs especially about interrupt.

1. set intlocal field to zero for both DSPs

2. set int2cfg field to 0 for both DSPs

3. change the destination address from channel maping register to interrupt set/pending register. this address always should be interrupt set/pending register. you can not use this for other purpose.

4.  Check your mps index is perfectly matched with your interrupt vector array index and all other configuration is done successfully (use my code for comparison)

Albert 

Glad to see your reply, Albert!

As for your four suggestions , i think i did the same as the first two.

    FOR  the third, do you mean set/pending register  whose relative address is 0x14  in hyperlink module  when mentioning " interrupt set/pending register" ?  Yes, i am sure

i  tried 0x14.

   FOR the fouth,  yes , i set icidx the same index with ivector  and configed sien、inten "1" , as is why  DSP_B can receive interrupt packet.  

So , in your opinion , if i set mps 0, and Interrupt pointer value 0x14, and int2cfg "0"  then which register this interrupt packet goes to write, still  interrupt set/pending register ? the same as that when int2cfg is 1 ?

In your test, the destination address should be CIC0 system interrupt status raw/status register which is in 0x02600200 ~ 0x02600300 and int2cfg need to be set to zero for both DSPs.

So Albert you mean i can config Interrupt Pointer Register between 0x02600200 ~ 0x02600300,  and with proper mps value , then the received interrupt packet goes to write

 interrupt status raw/set  register ?

Yah, It is a good idea, i didn't try this configuration .

Thank you very much for your suggestions!

I'll try it tomorrow and give you feedback in time.

Hi, Albert,

Today i tried configure interrupt pointer register with 0x02600200, it still doesnt work , the interrupt packet doesnt write any  memory  in DSP_B,

so i still need your help about transfering interrupt packet that writes interrupt controller register in DSP_B.

Could you please try this issue in your devices?

Hey Albert,

To reach my goal , today i tried another way. I  maped  CIC0 register region as a segment into the hyperlink memory window, then tried to write registers in DSP_B through

hyperlink.  

 I succeeded in writing channel mapping registers , while failed in writting System Interrupt Status Raw/Set Register.

These two sets of registers are in the same memory segment , i just dont know why a part of it can be write, while another cannot be.

Thanks for your support and wish your reply.

Sincerely Kaba.

I'm not sure what is your ultimate purpose. is it changing channel mapping register or CIC0 system interrupt status raw/set register?  I don't know why your second method doesn't work for raw/set register. you may need to spend more of your time for detail debugging. theoretically, there is no reason to be blocked if those area is access free area. and I don't understand why you directly try to change the CIC0 interrupt registers, even though you can use hyperlink interrupt to control your application.

about your first method, currently,  I don't have enough time to run the test on my side because I have several other urgent jobs to be finished. Let me try that later when I have more time.

-albert

Hi Albert,

My ultimate purpose is to send interrupt packet from dsp_A  to dsp_B, and this interrupt packet interrupts a paticular core in DSP_B, and the index of this paticular

core  is determined by software in DSP_A.

TO achieve this goal above , i considered several methods below:

1.  send interrupt packet  from dsp_A to dsp_B, and this interrupt packet generates hyperlink module interrupt, which is mapped to system event whose event ID is 111.

But there is only one system event for hyperlink module output interrupt, so it seems impossibel to interrupt varous core flexibly  with only one system event as input.

2. so , i tried another method, set int2cfg to zero in dsp_B,  in order to let the interrupt packet go to write chip-level interrupt registers , however this doesnt work in  my

tests.

     But i still believe the reason TI design a int2cfg = 0 processing brach for hyperlink interrupt module is to make interrupt more flexible, which well meets my need.  so i

hope i can make this processing branch that interrupt packet writting cic regs work  one day.

3.  Then ,  as long as the above 2 methods dont work  and what i have achieved  is geting  interrupt  in  DSP_B  hyperlink module, in another word i have one system

interrupt.  So how to interrupt different core in DSP_B  with only one system interrupt?

This is why i tried to write channel mapping registers from dsp_A to dsp_B.  Because you know some channel is related to a paticular core, like 64,74,84,94

correspongding to core0-3 in c6670, so if i change the channel number for system interrupt 111 before sending interrupt packet , i think i can interrupt the paticular core

i want. and i did achieve this yesterday.

But for my application  this method is not the best , the best is the way using interrupt packet to write chip-level int registers.

Albert , if you have any suggestion about my ultimate purpose , please tell me.

Thanks you very much!

sincerely Kaba.

So your ultimate goal is accessing each Core level interrupt controller set/pend register and not  CIC0 registers. then you don't need to use 0x0260**** as the target address.  you can directly access each Core interrupt register address (use global level address of each Core). mps index 0 for core0, 1 for core1 ........

Anyway, I think the better solution is getting hyperlink interrupt and deliver it to all cores. CIC0 has one input from Hyperlink and it is broadcasted to all four cores (hard wired) and each CPU application can decide if it accepts the interrupt or not. we have total 32 bit for Hyperlink interrupt, so you can differentiate the interrupt like bit0 for Core0 and bit1 for Core1and so on... and your CPU application easily differentiate which event can be used for which core. I think this is better way  than delivering the interrupt directly to the specific Core interrupt controller with different destination path like you are thinking. isn't it acceptable?

Albert 

Hey Albert,

My ultimate goal is to interrupt  a core in target dsp, but through my tests about methods of interrupt packet writting cpintc regs、interrupt status raw/set regs, but failed.

And now i decide to achive my goal by writting channel mapping regs dynamically and it seems work well anyway although its not the best way.

Yes, i can interrupt all the cores in target dsp  each time and differentiate it from the status regs, but its not  so good in my application because there are too many interrupts

in my application, which i think can make the app more complex and spoil instruction pipeline.

Thank you for your support these days!

Sincerely kaba.

Hi,

I didn't get clear answer from DV team but I think there must be a problem from VBUS routing of incoming interrupt packet when the address is set to general controller. honestly, that feature was not tested on our AVV because no customer wanted to use that. anyway, sorry to give you inconvience about this.

BR,

Albert

Hi Albert,

Thank you very much for your reply.

Yes , i know your product is and should be customer oriented, its no problem.

But i still believe interrupt packet writting chip-level intc regs is a very good design and very usefull cauz it makes hyperlink

interrupt function much more flexible and efficient.

Sincerely,

Kaba.

I am also looking for the same. Any clear cut idea about whether it can be done or else, something like there is a hardware bug, so not possible with the current setup... Any sort of authorized statement? I tell this because, if its certain that its not possible,  then I would rather try to go with the QMSS way or the EDMA3 way.

regards,

Sijomon

Hi sijomon,

for this issue i havnt got any offical statement, but from the tests i have done there seems to be hardware bug in hyperlink interrupt package module( when used to write the other dsp's intc regs).

    actually i found another way to flexibly write interrupt to the other dsp, that is, to map the intc register region into hyperlink window, and then you could write the other dsp's intc regs the way you do in your side. And my software now runs well for a long time.

Hope this may help.

Hi All,

Hyperlink supports interrupt packet delivery to any internal interrupt controller in DSP in theory, but the availability depends on SOC level inner network design. until now, we haven't support that feature even though it is fully supported by Hyperlink IP level. there must be some reasons why our system and architecture guys didn't allow to use it, but currently we only physically support Hyperlink to Hyperlink interrupt packet delivery.

We'd better call it as "TI's decision" rather than "HW bug" 

sorry if I didn't give you the answer at proper timing.

Regards,

Albert  

Hi kabalagala,

Thanks for your prompt reply. Let me clarify myself. Is it that we setup one of the 64 receiver regions to point to the core interrupt controllers memory map is situated, and then do a remote register write to the the event set register of the core interrupt controller? Currently I am working with 2 6678 DSPs connected with hyperlink. Can you please help me out in finding out the memory mapped addresses for core interrupt controllers of each of the 8 cores of 6678. In data manual, the map for corepac int controller says 0180 0020h to 0180 002Ch maps to event set registers of the core. This is the address if we look from inside that particular core. To set these address from outside which all addresses we need to map?  

Hi Albert,

Sorry if I hurt your company's feelings. I frankly didn't mean that. But I would like to point out one thing. I sat around with this setup for around one month and then only I came to the conclusion that this method is not working. After reading the documents, I gave my higher ups, a tentative date of completion of 2 days. Then it went up for one full month. The hyperlink document is one of the most confusing documents I have ever read, you know? You may call it TI's decision, but it's no way our concern. At least had you conveyed it properly, then we would have gone for some other methods. With this statement, What I should conclude is as the following.

Even after reading TI's documents, I should not believe that whatever is given in the document need not be conclusive. There should be some internal policies with which part of the document can be invalid. If it works at one shot, you are lucky, else.....

Whatever I had to hear from my boss, let it die with me!

regards,

Sijomon India

Hi parakkal,

Yes, your understanding is almost right.

 Just one thing to correct, you setup one of the hyperlink regions pointing to CPINTC register memory of the remote dsp, then you could freely set the event flag of remote dsp and corresponding interrupt is generated.

Note: 1. it's CPINTC( chip level intc), not corepac intc, the address should be 0x26xxxx, you could check from the mannual.  And in this case you set the event flag, of course you have to do some other work such as map the event to a proper channel and then to a proper interrupt id in corepac level.

          2. Actually there is only one system event dedicated for hyperlink, so if you want to send more interrupts(probably to each core), you have to use more system events. what i did is to use one of the system event that i don't use in my application, such as srio, or anything else. This is up to your application.

Hi Kabalagala, 

Thanks for your timely advice. Then I should route the secondary events from the CIC to Corepac, am I right? From there it's quite straight forward, it seems. Routines are available with sys/bios package. i think I would make use of those routines then, instead of directly manipulating the registers. I think I am quite clear now. I rule out the direct event setting of the corepac int controller area then.

Thanks,