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Basic query about Interrupt Controller behaviour

Akash Bhatnagar93368
Prodigy 130 points

Hi all,

I am using TI DSP 6487 for our project and currently working on EDMA3 module of this DSP. I have initialize properly the EDMA3 module over single core and get it to work.

While executing same code over multiple cores, I got into doubt that what happens when the Global Transfer Completion interrupt occurs for any of the cores? Whether all three cores receive the interrupt?

I have configured common ISR (without any core checks in it) to EDMA3 global CC event to interrupt line 8. Unfortunately, i am not able to find out any specific TEXT lines in any of related documents,  specifying interrupt controller behavior on Multiple Cores.

Here is sample code i am using to configure ISR.

void isr_install_edma_isr(isr_cb_t edma_isr)
{
    HWI_Attrs hwi_attrs = HWI_ATTRS;

    HWI_disable();

    /* Map EDMA interrupt */

    HWI_eventMap(8, CSL_INTC_EVENTID_EDMA3CC_GINT);

    /* Plug ISR into BIOS dispatcher */

    HWI_dispatchPlug(8, (Fxn) edma_isr, -1, &hwi_attrs);

    /* Enable interrupts */

    C64_clearIFR(1 << 8);
    C64_enableIER(1 << 8);

    HWI_enable();
}

  • 0
    TI__Guru* 84110 points

    Akash,

    The TCI6487 is not supported through the E2E Forum. Instead, we have other direct support paths for you to get support tailored to your business and market segment. Please contact your TI sales representative for more information, if you do not have the names or contacts available already.

    I recommend against using the same EDMA3 interrupt source for all three cores. You can do this, to the best of my knowledge, but there can be problems since all three cores will want to deal with the interrupt in the same way, which means trying to read and clear the same IPR register.

    The better method is to use a different Shadow Region for each of the three cores and let each core get an interrupt only for the EDMA3 channels that are intended for that one core. If a single channel should cause an interrupt on all three cores, let one of the cores receive the EDMA3 interrupt and then send an IPC interrupt the other two (or to all three if the ISRs need to be more closely synchronized). This phased interrupt technique will cause extra latency, but would be a clean method.

    I can imagine problems with sending the same interrupt to all three, so if you decide to go the single interrupt route, please be very careful and test the system thoroughly. And talk it over with your TCI6487 support team.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 130 points

    Thanks RandyP for conclusive reply.

    Shadow region will be a good Idea (though add some complexity to my code). Actually I am using a group of EDMA3 channels (say 75,76,77) to configure EDMA3 Parameters of other channels (Peripheral dedicated).These channels will always lie into some fixed shadow region. So for different shadow regions I have to choose different configuring channels (lets say 1,2,3 for region 1).

    But atleast interrupt/events of EDMA3 will be different for all cores.

    As for your suggestion, "allow one core to signal other using IPC", I think that may cause problems in my scenario. I my scenario,all cores of 6487 will be independent and running same code. If core 0 become down somehow or got hanged, then it affects other cores too. Am i right?

    Thanks

  • 0 in reply to Akash Bhatnagar93368
    TI__Guru* 84110 points

    Akash,

    Akash Bhatnagar93368 said:
    I am using a group of EDMA3 channels (say 75,76,77) to configure EDMA3 Parameters of other channels (Peripheral dedicated)..

    This is not clear to me, but you may be finished with your questions and have no need to explain further. It is not clear if the group of three channels 75, 76, 77 (which do not exist, there are only channels 0-63) are one per core or an arbitrary number of channels for a purpose. It is not clear how you would use channels to configure the PARAM of other channels. If you do wish to discuss this, please continue the thread or start a new one, or contact your TCI6487 support team.

    Akash Bhatnagar93368 said:
    If core 0 become down somehow or got hanged, then it affects other cores too. Am i right?

    Since you cannot have every core equally involved in using all system resources, you will always have a problem with dependencies between the cores.

    Regards,
    RandyP