Hello,
we keep having various problems when integrating our dsp application with the FPGA on our custom board containing two 6678 and one FPGA. We need to be able to see exactly what is going on on both sides of the SRIO link so I'm trying to build as small "hello world"-like test application as possible. It runs on one DSP, one core, no OS, using the debugger.
My questions are:
(1) Is there any example of doing the above using only LSU-level code, without using interrupts? I can't find where to poll for the retrieved data.
(2) Our first goal is to have the FPGA sending data to the DSP(s). Due to the tight time plan, we need to choose the easiest-to-implement alternative of:
(a) FPGA sending data with DirectIO NWRITE (or NWRITE_R) and Doorbells
(b) DSP polling FPGA for data with NREADs (we CAN afford sacrificing one core to only do that...)
(c) FPGA sending data with Messages (type 11) (in this case we cannot avoid using the whole MultiCoreNavigator stuff, i.e. the LLD driver)
We have full control of the memory maps on both sides.
The actual data consists of small chunks of data (30-40 bytes) arriving in an unpredicable rate, peak rates are roughly 1 M packets/s, i.e. ~320 MBit/s.
The FPGA side will likely buffer up some "suitable" amount of packets and sending them as a much larger chunk to avoid wasting SRIO bandwidth.
All inputs and thoughts are appreciated!
BR Marty
