VPBE Digital out with soft OSD

are there any way to modify or use the current drv_display.c to ouput Digital 720p instead of NTSC analog? Please give me some explanation as your experiences. Thanks

Bioz,

Does the Appro hardware support component output?

-Renjith

www.pathpartnertech.com

hi,

Appro HW IPNC itself does not support Component output. I am porting the Software V2.6 into our HW which base on Appro hardware design.

The component output was mapped into VPBE Digital out, YCC 16 mode, and 720p. I am not professional in this field so I got a lot of troubles.

If you have any references, example or experiences in setting for this requirement please give me a hand.

thanks

Bioz,

I didn't understand the statement here "The component output was mapped into VPBE Digital out, YCC 16 mode, and 720p. I am not professional in this field so I got a lot of troubles." Are you using VPBE Digital output(LCD) or are using Component HD Video out YPbPr (using DACs)?

Also, as of IPNC stack only supports CVBS local video output(NTSC/PAL). To support Component output, there will be changes required right from the browser application and to the complete stack and drivers. Its not so easy to do. It will take an effort of around 8-10 weeks.

-Renjith

www.pathpartnertech.com

Hi Renjith,

as I know, VPBE support some type of interface such as Analog (SD or component), YCC 8, YCC 16, Parallel RGB ... We are using VPBE YCC 16bit, Digital output (LCD). In firmware testing pack which supplied by Appro has already some examples for Analog (SD and HD) checking but not for Digital out. We already success in Analog test.

In IPNC application, Appro only support NTSC analog out, but if we look deeply into drv_display.c (Avserver) and Davinci display driver (kernel), we can see many options for NTSC, Pal, Digital out 720P, 1080i, ... In my opinion, we just need to modify a bit in register setting, and display configuration to support digital out instead of NTSC analog. But I have no experience in this case, I tried and referenced many setting for VPBE digital out 720p using standard timing but I failed. 

Bioz,

Are you planning to use the same appro application? If so, the application is different layers. One from the browser ActiveX plugin needs to be changed and all across the stack. The driver already supports different display devices, but in IPNC stack its not completely tested as there is no hardware available on Appro board. The LCD driver that is supported currently on DM368 kernel is supporting the resolution 480x272. You've to change these driver for LCD support, but to add one more device in the complete stack, it will take time.

What is the resolution of the LCD panel in your device?

Hi,

Yes, we are planning to use appro app ver 2.6. Everything was working well now except Digital HD output. Definitively, We need to modify all system from web interface (local output setting to support NTSC, PAL, Digital ... ), IPNC Server, AVServer and Video display driver inside kernel. I have already prepared everything, now my problem is how to setup the VPBE register to support Digital out HD in kernel driver. For convenience, I am trying the setting in firmware test with code composer. By using current Appro EVM-dm368 HD loop back test, I am modifying it to support Digital out HD 720p instead of Analog out HD 720 P as current status. I again confirm that I have already successed in testing HD loop back for Analog component output, VPFE is working well. My question is How or which registers I should change to support Digital out HD 720p YCC 16 (LCD) in Code composer? Below is my current setting:

static void vpbe_init( )
{
Uint32 video_buffer = DDR_BASE + ( DDR_SIZE / 2 );
Uint32 basep_x;
Uint32 basep_y;
Uint32 width;
Uint32 height;
Uint32 test;

width = 1280;
height = 720;

/*
* Setup clocking / DACs
*/
//VPSS_CLKCTL = 0x00000038; // Enable DAC and VENC clock, use PLL2
VPSS_CLKCTL = 0x0a; // Enable DAC and VENC clock, use PLL2
// Select EXTCLK as video clock source
VPSS_VPBE_CLK_CTRL = 0x00000011; // Select enc_clk*1, turn on VPBE clk
VENC_CLKCTL = 0x00000011; // Enable venc & digital LCD clock
VENC_XHINTVL = 0x00000000; // Extend standard 720P horizontal timing

/*
* Setup OSD
*/

OSD_MODE = 0x00fc; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0x0000; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0x0000;
OSD_RECTCUR = 0x0000;
OSD_EXTEND_MODE = 0x0000;

OSD_VIDWIN0OFST = 0x1000 | width >> 4;
OSD_VIDWINADH = 0x0000;
OSD_OSDWIN0ADL = 0x0000;
//OSD_BASEPX = 0x0000;
//OSD_BASEPY = 0x0000;
OSD_BASEPX = BASEX720P;
OSD_BASEPY = BASEY720P;

//OSD_VIDWIN0XP = 0x0100;
//OSD_VIDWIN0YP = 0x0000;
OSD_VIDWIN0XP = 220;
OSD_VIDWIN0YP = 25;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height;

OSD_OSDWIN0XP = 220;
OSD_OSDWIN0YP = 25;
OSD_OSDWIN0XL = DISP_XRES720P;
OSD_OSDWIN0YL = DISP_YRES720P;

OSD_VIDWINMD = 0x00000001; // Disable vwindow 1 and enable vwindow 0
// Frame mode with no up-scaling
VENC_VDPRO = 0x0000; // Normal mode, not colorbars
VENC_DACTST = 0x0000; // Power on DACs
VENC_DACSEL = 0x0543; // Component out on DACs

VENC_HSPLS=BASEX720P;
VENC_VSPLS=BASEY720P;
//VENC_HINT=1649;
VENC_HINTVL = 1649;
VENC_HSTART=300;
VENC_HVALID=DISP_XRES720P;
//VENC_VINT=749;
VENC_VINTVL = 749;
VENC_VSTART=26;
//VENC_VSTART = 0x10;
VENC_VVALID=DISP_YRES720P;
VENC_HSDLY=0;
VENC_VSDLY=0;
VENC_YCCCTL=0;
VENC_VSTARTA=0;

//VENC_DCLKCTL = 0x8800;
//VENC_DCLKCTL = 0x8000;
VENC_DCLKCTL = 0x0800;
VENC_DCLKPTN0 = 0x0001;
VENC_DCLKPTN1= 0;
VENC_DCLKPTN2= 0;
VENC_DCLKPTN3= 0;
VENC_DCLKPTN0A= 2;
VENC_DCLKPTN1A= 0;
VENC_DCLKPTN2A= 0;
VENC_DCLKPTN3A= 0;
//VENC_DCLKHS= 0;
VENC_DCLKHSTT = 0;
//VENC_DCLKHSA= 1;
VENC_DCLKHSTTA = 1;
//VENC_DCLKHR= 0;
//VENC_DCLKVS= 0;
//VENC_DCLKVR= 0;
VENC_RGBCTL=0;

VENC_DRGBX0 = 0x00000400;
VENC_DRGBX1 = 0x00000576;
VENC_DRGBX2 = 0x00000159;
VENC_DRGBX3 = 0x000002cb;
VENC_DRGBX4 = 0x000006ee;

VENC_ACCTL = 0;
VENC_CVBS = 0;
VENC_CMPNT = 0;

//VPSS_MISR_CTRL = 0x0003;
VENC_VIOCTL = 0x6000;
//VENC_VIOCTL = 0x3000;
VENC_YCCCTL |= 0x10;
VENC_LCDOUT = 0x0001;
VENC_SYNCCTL = 0x0003;
VENC_OSDCLK0 = 0x00000000;
VENC_OSDCLK1 = 0x00000001;
VENC_OSDHADV = 0;
//VENC_VMOD = 0x0dc0; // 2111
VENC_VMOD = 0x05c0; // 2111
//VENC_VMOD = 0x0111;
//VENC_VMOD = 0x1001;

//VENC_SYNCCTL = (VENC_SYNCCTL_SYEV | VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL | VENC_SYNCCTL_VPL);
// ~Bioz
}

Please give me some hint to correct it. Thanks

Bioz,

Before setting OSD registers, can you enable OSD color bars in VMOD register and check whether you are able to see the color bars on the LCD. This will help you in validating the LCD timings properly. Also, if you are not seeing anything just send a description/snapshot of what exactly is happening with the LCD.

hi,

I am now already success in firmware test with below code:

static void vpbe_init( )
{
Uint32 video_buffer = DDR_BASE + ( DDR_SIZE / 2 );
Uint32 basep_x;
Uint32 basep_y;
Uint32 width;
Uint32 height;
Uint32 test;

width = 1280;
height = 720;

/*
* Setup clocking / DACs
*/
//VDAC_CONFIG = 0x081141EF; // Take DACs out of power down mode, enable HD component out
VPSS_CLKCTL = 0x00000038; // Enable DAC and VENC clock, use PLL2
//VPSS_CLKCTL = 0x00000028; // Enable DAC and VENC clock, use PLL2
// Select EXTCLK as video clock source
VPSS_VPBE_CLK_CTRL = 0x00000011; // Select enc_clk*1, turn on VPBE clk
//VPSS_VPBE_CLK_CTRL = 0x00000019; // Select enc_clk*1, turn on VPBE clk
VENC_CLKCTL = 0x00000011; // Enable venc & digital LCD clock
//VENC_CLKCTL = 0x00000010; // Enable venc & digital LCD clock
VENC_XHINTVL = 0x00000000; // Extend standard 720P horizontal timing

/*
* Setup OSD
*/

OSD_MODE = 0x00fc; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0x0000; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0x0000;
OSD_RECTCUR = 0x0000;
OSD_EXTEND_MODE = 0x0000;

OSD_VIDWIN0OFST = 0x1000 | width >> 4;
OSD_VIDWINADH = 0x0000;
OSD_OSDWIN0ADL = 0x0000;
//OSD_BASEPX = 0x0000;
//OSD_BASEPY = 0x0000;
OSD_BASEPX = BASEX720P;
OSD_BASEPY = BASEY720P;

//OSD_VIDWIN0XP = 0x0100;
//OSD_VIDWIN0YP = 0x0000;
OSD_VIDWIN0XP = 220;
OSD_VIDWIN0YP = 25;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height;

//OSD_OSDWIN0XP = 220;
//OSD_OSDWIN0YP = 25;
//OSD_OSDWIN0XL = DISP_XRES720P;
//OSD_OSDWIN0YL = DISP_YRES720P;

OSD_VIDWINMD = 0x00000001; // Disable vwindow 1 and enable vwindow 0
// Frame mode with no up-scaling
VENC_VDPRO = 0x0000; // Normal mode, not colorbars
VENC_DACTST = 0x0000; // Power on DACs
VENC_DACSEL = 0x0543; // Component out on DACs

// Timing
VENC_HSPLS=0x50;
VENC_HINTVL = 1280 + 300 + 70 - 1;
VENC_HSTART=300;
VENC_HVALID=1280;

VENC_VSPLS=0x5;
VENC_VINTVL = 720 + 26 + 3;
VENC_VSTART=26;
VENC_VVALID=720;
// ~Timing

VENC_DCLKCTL = 0x0800; // 0x8000; 0x0800; 0x8800
VENC_DCLKPTN0 = 0x0001;

VPSS_MISR_CTRL = 0x0003;
VENC_VIOCTL = 0x6000; // 0x2000 - 0x6000
VENC_LCDOUT = 0x0001; // 0x0001
VENC_SYNCCTL = 0x0103; // 0x000f 0x0003

VENC_OSDCLK0 = 0x00000000;
VENC_OSDCLK1 = 0x00000001; // 0x00000003
VENC_OSDHADV = 0;
VENC_VMOD = 0x05c1; // 0x05c3 - 0x0dc1 - 0x0111 - 0x1c3
//VENC_YCCCTL = 0x02; // add for embedded sync

//VENC_YCOLVL = 0x00000000;

//VENC_SYNCCTL = (VENC_SYNCCTL_SYEV | VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL | VENC_SYNCCTL_VPL);
// ~Bioz
}

We can see correct data output on LCD. But when I apply same setting for kernel in davinci_platform.c and IPNC soft was modified to change the resolution,  we saw this result:

by checking oscilla I can see that Vsync, hSync and pixel clock my be correct, but Cout and Yout didn't have signal. Do you have any idea?

Can you dump and all the relevant register settings in kernel and compare with u-boot? Also did you check the values in of PINMUX registers as well. As I suggested before, you can try enabling the color bars in VENC, and will help you debug the problem faster and better