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What is the relationship between cycles and clock freq?

Robert W
Mastermind 7100 points

 

 

There are some algorithm benchmark in the following link:

http://www.ti.com/sc/docs/products/dsp/c6000/62bench.htm

For example, for FIR-coefficients a multiple of 4, it needs: M*(N+8)/2 + 6 For N=32 and M=100 2006 cycles or 10.03 �sec. On my computer, the letter before 'sec' does not display correct. Although I can guess (is it us?) from a simple calculation, I want get confirmed from you. The DSP clock frequency is:

2006(cycles)/8(cycles per clock?)/10.03 (uS)=1600 (MHz)

The main concern to me is: one clock generates 8 cycles in DSP. It it right?

Thanks. 

 

 

  • 0
    Mastermind 7395 points

    The 64x core has eight functional units working in parallel, that is why during one clock you can execute up to 8 instructions simultaneously.

  • 0 in reply to Avi Chami1
    TI__Guru* 84110 points

    Robert,

    Albert's statement is correct for all C6000 devices, but is not what you use for your question on the meaning of the benchmark.

    The micro symbol does not display in IE8, either.

    Robert W said:
    2006(cycles)/8(cycles per clock?)/10.03 (uS)=1600 (MHz)

    "Cycles" in the benchmarks is equivalent to the inverse of the core clock frequency. In one clock cycle, from 1 to 8 instructions may be executed in parallel, but this is considered one instruction cycle.

    The /8 should be removed from your equation, and you will get 200 MHz as the apparent clock frequency at which this benchmark was run.

    Since this page is named 62bench, it must be based on the original C62xx architecture. Please refer to the benchmarks numbers in the DSPLIB documentation for whichever device you plan to use. I suspect the numbers will be better due to architecture improvements over the years.

    Also, newer DSPs will run at higher clock frequencies, up to 1.25GHz, for example, in the C66xx family.

    Regards,
    RandyP