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Plz Help to understand Overall picture of captured data streaming on DM8168.

P W
Intellectual 580 points

I am trying to understand architecture of VPSS related to HDVICPs for DM8168. I don't have much firmware background.

What I managed to do so far is to load load-hd-v4l2-firmware.sh on my DM8168-EVM, and managed to capture 1080p60 video through Y Pr Pb ports on daughter board and encode it to a file, using Gstreamer pipeline code:

gst-launch v4l2src always-copy=false queue-size=12 num-buffers=2000 ! 'video/x-raw-yuv-strided,format=(fourcc)NV12,width=1920,height=1080,framerate=(fraction)60/1' ! omxbufferalloc numBuffers=12 ! omx_h264enc bitrate=5000000 ! gstperf ! filesink location=v4l2cap.h264

But I want to know how many HDVICPs are actively encoding when I used the above Gstreamer pipeline. So I start looking at the Figure1 and Figure2 to understand system architecture of the DM8168.


.


Q1. I can see there are several video pipelines and graphic pipelines in Figure1. What does this pipeline exactly mean? (Is this a software path for data stream to pass through?) And what is the difference between Video and Graphic pipeline?

Q2. Does one of these graphic or video pipelines have something to do with capturing driver? If I type the above Gstreamer command, I know the video image is coming in through v4l2 driver. But which pipeline does this captured video stream go?

Q3. Once the video stream passes one of pipelines, the video stream should be encoded with H.264 codec to be stored in a file. But in Figure1, I only see four Encoder blocks right before some kind of output ports?(DVO0, HDComp, SD) I think basically I want to know where my captured video stream goes through on Figure1.

Q4. Where does HDVICP coprocessor actually do the work? From my shallow understanding, I think it should be helping the encoder blocks to encode. Is this correct? If only one Encoder block is used, is only one HDVICP doing the encoding?
.


Sorry for asking many questions. But I have gone through all the user guides(VPSS , video driver guides, SDGuide, etc...) to understand overall pictures, but the guides seem assume readers have some background in embeded system and firmware which I don't. Any your replies would be much appreciatd.

Figure1

Figure2

  • 0
    TI__Mastermind 20245 points

    Hi,

    Answers inline,

    P W said:
    Q1. I can see there are several video pipelines and graphic pipelines in Figure1. What does this pipeline exactly mean? (Is this a software path for data stream to pass through?) And what is the difference between Video and Graphic pipeline?

    A1. Each pipeline (video and grahics) can take data from memory and display it using the display devices. Optional data can be blended in compositor module.  Main difference between video and graphics pipeline is that video can take YUV data and graphics can take RGB data.

    P W said:
    Q2. Does one of these graphic or video pipelines have something to do with capturing driver? If I type the above Gstreamer command, I know the video image is coming in through v4l2 driver. But which pipeline does this captured video stream go?

    A2. Capture path is entirely different, video and graphics has nothing to do with it.

    P W said:
    Once the video stream passes one of pipelines, the video stream should be encoded with H.264 codec to be stored in a file. But in Figure1, I only see four Encoder blocks right before some kind of output ports?(DVO0, HDComp, SD) I think basically I want to know where my captured video stream goes through on Figure1.

    A3 Blocks shown as encoder is video signal encoder, which encodes Digital video signals in various protocols like HDMI, Analog etc. While we have video data encoders, which works on video data and encodes raw YUV data into H.264 or alike encoding. So although both are named as encoders, one is video signal encoder while other is video data encoder.

    P W said:
    Where does HDVICP coprocessor actually do the work? From my shallow understanding, I think it should be helping the encoder blocks to encode. Is this correct? If only one Encoder block is used, is only one HDVICP doing the encoding?
    .

    A4 Yes, you are absolutely correct.

    Regards,

    Hardik Shah

  • 0 in reply to HardikShah
    Intellectual 580 points

    Thank you so much for your answers~!! Hardik.