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Link RAM of QMSS

guoping Lee
Expert 1010 points

Hi everyone .

when I look into the KeyStone Architecture Multicore Navigator User Guide,I am confused with the Link RAM.How does one descriptor map to the Link RAM?what does the relation between the index and address?thanks 

  • 0
    TI__Intellectual 1880 points

    Hi Guoping,

    I am checking with the user guide owner on the Linking RAM details and I will get back with you as soon as possible.

  • 0 in reply to Derek Brown
    TI__Intellectual 1880 points

    Hi Guoping,

    The linking RAM is used internally by the QMSS to store how descriptors are linked together. Each descriptor gets mapped to the linking RAM in order: descriptor 0 gets mapped to linking RAM index 0, descriptor 1 gets mapped to linking RAM index 1, and etc. In your program, you only need to point the QMSS to the linking RAM memory through the linking RAM Base and Size registers, and the QMSS hardware will maintain the linking RAM memory. Since the QMSS owns and maintains the linking RAM memory, modifying the contents of the linking RAM will cause errors. This region should never be modified by the program.

    Although this information does not currently exist in the Multicore Navigator user guide, it is described in the Keystone training modules.

    The linking RAM details that you are looking for are covered in slide 6 in the QMSS training.