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UART Break Signal Settings

Marko Vico
Prodigy 150 points


I'm using PSP 1_10_03 with DM6437 and want to configure UART0  to work with PSP driver, but don't know how to specify the UART driver settings to generate a 'BREAK' signal before each data transfer on Tx line of DSP UART bus.

How to adjust setting in PSP UART driver to enable 'BREAK' signal generation?

Regards,

Marko Vico

 

  • 0
    TI__Expert 5500 points

    Hi Marko,

    The feature you are looking for is not supported by the PSP driver.

    Regards,

    Raghavendra

  • 0 in reply to Raghavendra Maddikery
    Prodigy 150 points

    Thank's Raghavendra,

    What would be the way around to enable BREAK signal.

    Also, can I control the length of the BREAK signal. If it's possible, how to do it?

    Finally, can I control the gap time between the BREAK signal and the Data sequence coming after the BREAK signal?

     

    I'm using CCS v3.3    Integrated Development 5.98.0.393

    BIOS 7.41.10.36

    Code Generation Tools v7.2.7

    PSP 1.10.03

    DSP : DM6437

    Regards,

    Marko

  • 0 in reply to Marko Vico
    TI__Expert 5500 points

    Hi Marko,

    I have not tried this. But,

    If you refer the UART SPRU, the Break signal can be enabled/generated by setting Line Control Register(LCR[6]) BC.

    Use the cslr's to set/modify a particular bit in the UART registers in your application.

    cslr files are placed in - pspdrivers_1_10_03\packages\ti\sdo\pspdrivers\soc\dm6437\dsp

    You can refer the Uart_example.c file (placed in - pspdrivers_1_10_03\packages\ti\sdo\pspdrivers\soc\dm6437\examples\uart\src) which demonstrates CSL UART register layer usage.

    Best Regards,

    Raghavendra

  • 0 in reply to Raghavendra Maddikery
    Prodigy 150 points
    Hi Raghavendra,
     
    I modified code accordingly  to generate Brake signal, and now it comes to the uart bus.
     
    Finally, how can I control the Gap between the Break Signal and the Data sequence which is coming after the Break Signal?
     
    I tried to insert delay, but it didn't help. Also i tried to use TSK_sleep(1) { 1 mSec }  to make this gap but it didn't help either.
     
    here is the code snippet :
     
    if(ioHandle->devHandle->instanceId == 0){               // Break Generation for Device ID #0 ( UART0 )
       while (CSL_FEXT(ioHandle->devHandle->regs->LSR, UART_LSR_TEMT) == 0){   }
       CSL_FINST(ioHandle->devHandle->regs->LCR, UART_LCR_BC, ENABLE);     
        ioHandle->devHandle->regs->THR = 0x00; // transfer a character                               // The Length of the Break signal is 2 Characther trasfer time.
        ioHandle->devHandle->regs->THR = 0x00; // transfer a character                               // The Length of the Break signal is 2 Characther trasfer time
       while (CSL_FEXT(ioHandle->devHandle->regs->LSR, UART_LSR_TEMT) == 0){   }
       CSL_FINST(ioHandle->devHandle->regs->LCR, UART_LCR_BC, DISABLE);
      }
     
      // I have tried to insert Delay here in order to increase Gap between Break signal and the Data Sequence but it didn't work.
     
      EDMA3_DRV_enableTransfer(ioHandle->hEdma, ioHandle->ChId, EDMA3_DRV_TRIG_MODE_EVENT);
     
     
    UART1 Tx Break Signal Gap and Data sequence

    UART1 Tx Break Signal + enlarged Gap and Data sequence

     

  • 0 in reply to Marko Vico
    TI__Mastermind 18320 points

    Marko,

    This thread has now run past the scope of the PSP driver library and the knowledge of the PSP team.  I have moved this thread over to the DM64xx forum in hopes that you will get a faster resolution there.

    Dave