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Problem with clock

Jay Gowdy81418
Intellectual 810 points
Other Parts Discussed in Thread: OMAP-L138, SYSBIOS, OMAPL138

I am working on a custom OMAP-L138 board.   We have been working bare-metal code on the ARM core and SysBios on the DSP core, and are trying to move to use SysBios on the ARM core.

I am using the project generated in CCS5 by going to New CCS Project, and selecting the SYS/BIOS->Generic Examples->Task Mutex example, with a custom platform derived from the ARM OMAPL138 where all the code/data/stack are put in DDR.   I am using a GEL file which sets up the clocks and power the same way our working bare-metal code does:  405MHz system clock with 297MHz mDDR (and the custom platform frequency is also set to 405), with most things enabled.

So, I get the code to load and start running, but it appears that Clock_getTicks() always returns 0.   Consistent with this is that Task_sleep hangs forever.

Is there something I may have done in setting up the PLL and PSC's in my GEL files that could have done this?  Any suggestions on how to proceed?

I am using

  • CCS5.1.1.00031
  • SYS/BIOS 6.33.03.33
  • XDC tools 3.23.01.43

and I have made no modifications to the sample code beyond using my custom platform.

My GEL file is as follows,

#define PLL0_BASE       0x01C11000                              /*SYSTEM PLL BASE ADDRESS*/
#define PLL0_PID        *(unsigned int*) (PLL0_BASE + 0x00)     /*PID*/
#define PLL0_FUSERR     *(unsigned int*) (PLL0_BASE + 0xE0)     /*x*FuseFarm Error Reg*/
#define PLL0_RSTYPE     *(unsigned int*) (PLL0_BASE + 0xE4)     /*Reset Type status Reg*/
#define PLL0_PLLCTL     *(unsigned int*) (PLL0_BASE + 0x100)    /*PLL Control Register*/
#define PLL0_OCSEL      *(unsigned int*) (PLL0_BASE + 0x104)    /*OBSCLK Select Register*/
#define PLL0_SECCTL     *(unsigned int*) (PLL0_BASE + 0x108)    /*PLL Secondary Control Register*/
#define PLL0_PLLM       *(unsigned int*) (PLL0_BASE + 0x110)    /*PLL Multiplier*/
#define PLL0_PREDIV     *(unsigned int*) (PLL0_BASE + 0x114)    /*Pre divider*/
#define PLL0_PLLDIV1    *(unsigned int*) (PLL0_BASE + 0x118)    /*Divider-1*/
#define PLL0_PLLDIV2    *(unsigned int*) (PLL0_BASE + 0x11C)    /*Divider-2*/
#define PLL0_PLLDIV3    *(unsigned int*) (PLL0_BASE + 0x120)    /*Divider-3*/
#define PLL0_OSCDIV1    *(unsigned int*) (PLL0_BASE + 0x124)    /*Oscilator Divider*/
#define PLL0_POSTDIV    *(unsigned int*) (PLL0_BASE + 0x128)    /*Post Divider*/
#define PLL0_BPDIV      *(unsigned int*) (PLL0_BASE + 0x12C)    /*Bypass Divider*/
#define PLL0_WAKEUP     *(unsigned int*) (PLL0_BASE + 0x130)    /*Wakeup Reg*/
#define PLL0_PLLCMD     *(unsigned int*) (PLL0_BASE + 0x138)    /*Command Reg*/
#define PLL0_PLLSTAT    *(unsigned int*) (PLL0_BASE + 0x13C)    /*Status Reg*/
#define PLL0_ALNCTL     *(unsigned int*) (PLL0_BASE + 0x140)    /*Clock Align Control Reg*/
#define PLL0_DCHANGE    *(unsigned int*) (PLL0_BASE + 0x144)    /*PLLDIV Ratio Chnage status*/
#define PLL0_CKEN       *(unsigned int*) (PLL0_BASE + 0x148)    /*Clock Enable Reg*/
#define PLL0_CKSTAT     *(unsigned int*) (PLL0_BASE + 0x14C)    /*Clock Status Reg*/
#define PLL0_SYSTAT     *(unsigned int*) (PLL0_BASE + 0x150)    /*Sysclk status reg*/
#define PLL0_PLLDIV4    *(unsigned int*) (PLL0_BASE + 0x160)    /*Divider 4*/
#define PLL0_PLLDIV5    *(unsigned int*) (PLL0_BASE + 0x164)    /*Divider 5*/
#define PLL0_PLLDIV6    *(unsigned int*) (PLL0_BASE + 0x168)    /*Divider 6*/
#define PLL0_PLLDIV7    *(unsigned int*) (PLL0_BASE + 0x16C)    /*Divider 7*/


#define PLL1_BASE       0x01E1A000                              /*SYSTEM PLL1 BASE ADDRESS*/
#define PLL1_PID        *(unsigned int*) (PLL1_BASE + 0x00)     /*PID*/
#define PLL1_FUSERR     *(unsigned int*) (PLL1_BASE + 0xE0)     /*x*FuseFarm Error Reg*/
#define PLL1_RSTYPE     *(unsigned int*) (PLL1_BASE + 0xE4)     /*Reset Type status Reg*/
#define PLL1_PLLCTL     *(unsigned int*) (PLL1_BASE + 0x100)    /*PLL Control Register*/
#define PLL1_OCSEL      *(unsigned int*) (PLL1_BASE + 0x104)    /*OBSCLK Select Register*/
#define PLL1_SECCTL     *(unsigned int*) (PLL1_BASE + 0x108)    /*PLL Secondary Control Register*/
#define PLL1_PLLM       *(unsigned int*) (PLL1_BASE + 0x110)    /*PLL Multiplier*/
#define PLL1_PREDIV     *(unsigned int*) (PLL1_BASE + 0x114)    /*Pre divider*/
#define PLL1_PLLDIV1    *(unsigned int*) (PLL1_BASE + 0x118)    /*Divider-1*/
#define PLL1_PLLDIV2    *(unsigned int*) (PLL1_BASE + 0x11C)    /*Divider-2*/
#define PLL1_PLLDIV3    *(unsigned int*) (PLL1_BASE + 0x120)    /*Divider-3*/
#define PLL1_OSCDIV1    *(unsigned int*) (PLL1_BASE + 0x124)    /*Oscilator Divider*/
#define PLL1_POSTDIV    *(unsigned int*) (PLL1_BASE + 0x128)    /*Post Divider*/
#define PLL1_BPDIV      *(unsigned int*) (PLL1_BASE + 0x12C)    /*Bypass Divider*/
#define PLL1_WAKEUP     *(unsigned int*) (PLL1_BASE + 0x130)    /*Wakeup Reg*/
#define PLL1_PLLCMD     *(unsigned int*) (PLL1_BASE + 0x138)    /*Command Reg*/
#define PLL1_PLLSTAT    *(unsigned int*) (PLL1_BASE + 0x13C)    /*Status Reg*/
#define PLL1_ALNCTL     *(unsigned int*) (PLL1_BASE + 0x140)    /*Clock Align Control Reg*/
#define PLL1_DCHANGE    *(unsigned int*) (PLL1_BASE + 0x144)    /*PLLDIV Ratio Chnage status*/
#define PLL1_CKEN       *(unsigned int*) (PLL1_BASE + 0x148)    /*Clock Enable Reg*/
#define PLL1_CKSTAT     *(unsigned int*) (PLL1_BASE + 0x14C)    /*Clock Status Reg*/
#define PLL1_SYSTAT     *(unsigned int*) (PLL1_BASE + 0x150)    /*Sysclk status reg*/
#define PLL1_PLLDIV4    *(unsigned int*) (PLL1_BASE + 0x160)    /*Divider 4*/
#define PLL1_PLLDIV5    *(unsigned int*) (PLL1_BASE + 0x164)    /*Divider 5*/
#define PLL1_PLLDIV6    *(unsigned int*) (PLL1_BASE + 0x168)    /*Divider 6*/
#define PLL1_PLLDIV7    *(unsigned int*) (PLL1_BASE + 0x16C)    /*Divider 7*/
#define PLL1_PLLDIV8    *(unsigned int*) (PLL1_BASE + 0x170)    /*Divider 8*/
#define PLL1_PLLDIV9    *(unsigned int*) (PLL1_BASE + 0x174)    /*Divider 9*/
#define PLL1_PLLDIV10   *(unsigned int*) (PLL1_BASE + 0x178)    /*Divider 10*/
#define PLL1_PLLDIV11   *(unsigned int*) (PLL1_BASE + 0x17C)    /*Divider 11*/
#define PLL1_PLLDIV12   *(unsigned int*) (PLL1_BASE + 0x180)    /*Divider 12*/
#define PLL1_PLLDIV13   *(unsigned int*) (PLL1_BASE + 0x184)    /*Divider 13*/
#define PLL1_PLLDIV14   *(unsigned int*) (PLL1_BASE + 0x188)    /*Divider 14*/
#define PLL1_PLLDIV15   *(unsigned int*) (PLL1_BASE + 0x18C)    /*Divider 15*/
#define PLL1_PLLDIV16   *(unsigned int*) (PLL1_BASE + 0x190)    /*Divider 16*/

/*PSC Module Related Registers*/
#define PSC0_BASE       0x01C10000
#define PSC1_BASE       0x01E27000

#define PSC0_MDCTL      (PSC0_BASE+0xA00)
#define PSC0_MDSTAT     (PSC0_BASE+0x800)
#define PSC0_PTCMD      *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT     *(unsigned int*) (PSC0_BASE + 0x128)

#define PSC1_MDCTL      (PSC1_BASE+0xA00)
#define PSC1_MDSTAT     (PSC1_BASE+0x800)
#define PSC1_PTCMD      *(unsigned int*) (PSC1_BASE + 0x120)
#define PSC1_PTSTAT     *(unsigned int*) (PSC1_BASE + 0x128)

#define LPSC_EDMA_CC0    0
#define LPSC_EDMA_TC0    1
#define LPSC_EDMA_TC1    2
#define LPSC_EMIFA       3   /*PSC0*/
#define LPSC_SPI0        4   /*PSC0*/
#define LPSC_MMCSD0      5   /*PSC0*/
#define LPSC_ARM_AINTC   6
#define LPSC_ARM_RAMROM  7   /*PSC0*/
// LPSC #8 not used
#define LPSC_UART0       9   /*PSC0*/
#define LPSC_SCR0        10
#define LPSC_SCR1        11
#define LPSC_SCR2        12
// LPSC #13 not used
#define LPSC_ARM         14  /*PSC0*/
#define LPSC_DSP         15  /*PSC0*/

#define LPSC_EDMA_CC1    0
#define LPSC_USB20       1   /*PSC1*/
#define LPSC_USB11       2   /*PSC1*/
#define LPSC_GPIO        3   /*PSC1*/
#define LPSC_UHPI        4   /*PSC1*/
#define LPSC_EMAC        5   /*PSC1*/
#define LPSC_DDR         6   /*PSC1*/
#define LPSC_MCASP0      7   /*PSC1*/
#define LPSC_SATA        8   /*PSC1*/
#define LPSC_VPIF        9   /*PSC1*/
#define LPSC_SPI1        10  /*PSC1*/
#define LPSC_I2C1        11  /*PSC1*/
#define LPSC_UART1       12  /*PSC1*/
#define LPSC_UART2       13  /*PSC1*/
#define LPSC_MCBSP0      14  /*PSC1*/
#define LPSC_MCBSP1      15  /*PSC1*/
#define LPSC_LCDC        16  /*PSC1*/
#define LPSC_EPWM        17  /*PSC1*/
#define LPSC_MMCSD1      18
#define LPSC_UPP         19
#define LPSC_ECAP        20
#define LPSC_EDMA_TC2    21
// LPSC #22-23 not used
#define LPSC_SCR_F0      24
#define LPSC_SCR_F1      25
#define LPSC_SCR_F2      26
#define LPSC_SCR_F6      27
#define LPSC_SCR_F7      28
#define LPSC_SCR_F8      29
#define LPSC_BR_F7       30
#define LPSC_SHARED_RAM  31

/*DDR MMR Declaration*/

#define EMIF3A_SDRAM_CFG   0xB0000000
#define VTPIO_CTL          *(unsigned int*)(0x01E2C000)                  // VTPIO_CTL Register
#define EMIF3A_REVID       *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x00)      //EMIF Module ID and Revision Register
#define EMIF3A_SDRSTAT     *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x04)      //SDRAM Status Register
#define EMIF3A_SDCR        *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x08)      //SDRAM Bank Config Register
#define EMIF3A_SDRCR       *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x0C)      //SDRAM Refresh Control Register
#define EMIF3A_SDTIMR1     *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x10)      //SDRAM Timing Register1
#define EMIF3A_SDTIMR2     *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x14)      //SDRAM Timing Register2
#define EMIF3A_SDCR2       *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x1C)      //SDRAM Config Register2
#define EMIF3A_PBBPR       *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x20)      //VBUSM Burst Priority Register
#define EMIF3A_VBUSMCFG1   *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x28)      //VBUSM config Value1 Register
#define EMIF3A_VBUSMCFG2   *(unsigned int*)(EMIF3A_SDRAM_CFG + 0x2C)      //VBUSM config Value2 Register
#define EMIF3A_IRR         *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xC0)      //Interrupt Raw Register
#define EMIF3A_IMR         *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xC4)      //Interrupt Masked Register
#define EMIF3A_IMSR        *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xC8)      //Interrupt Mask Set Register
#define EMIF3A_IMCR        *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xCC)      //Interrupt Mask Clear Register
#define DDRPHYREV          *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xE0)      //DDR PHY ID and Revision Register
#define DDRCTL             *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xE4)      //DDR PHY Control 1 Register
#define DDRPHYCTL2         *(unsigned int*)(EMIF3A_SDRAM_CFG + 0xE8)      //DDR PHY Control 2 Register

#define EMIF3A_BASE_ADDR         0xC0000000
#define EMIF25_BASE_ADDR         0x40000000
#define EMIF25_CS2_BASE_ADDR     0x60000000
#define EMIF25_CS3_BASE_ADDR     0x62000000
#define EMIF25_CS4_BASE_ADDR     0x64000000
#define EMIF25_CS5_BASE_ADDR     0x66000000

/*EMIF2.5 MMR Declaration*/
#define EMIF25             0x68000000

#define EMIF25_AWAITCFG    *(unsigned int*)(EMIF25 + 0x04)
#define EMIF25_SDCFG       *(unsigned int*)(EMIF25 + 0x08)
#define EMIF25_SDREF       *(unsigned int*)(EMIF25 + 0x0C)
#define EMIF25_ACFG2       *(unsigned int*)(EMIF25 + 0x10)    //Async Bank1 Config Register
#define EMIF25_ACFG3       *(unsigned int*)(EMIF25 + 0x14)    //Async Bank2 Config Register
#define EMIF25_ACFG4       *(unsigned int*)(EMIF25 + 0x18)    //Async Bank3 Config Register
#define EMIF25_ACFG5       *(unsigned int*)(EMIF25 + 0x1C)    //Async Bank4 Config Register
#define EMIF25_SDTIM       *(unsigned int*)(EMIF25 + 0x20)    //SDRAM Timing Register
#define EMIF25_SRPD        *(unsigned int*)(EMIF25 + 0x3C)
#define EMIF25_NANDFCR     *(unsigned int*)(EMIF25 + 0x60)

/*GPIO MMR*/
#define GPIO_REG_BASE         (0x01E26000)
#define GPIO_BANK_OFFSET      (0x28)
#define GPIO_DAT_OFFSET       (0x04)
#define GPIO_SET_OFFSET       (0x08)
#define GPIO_CLR_OFFSET       (0x0C)
#define GPIO_BINTEN           *(unsigned int*)(GPIO_REG_BASE + 0x08)
#define GPIO_BANK01_BASE      (GPIO_REG_BASE + 0x10)
#define GPIO_BANK23_BASE      (GPIO_BANK01_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK45_BASE      (GPIO_BANK23_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK67_BASE      (GPIO_BANK45_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK8_BASE       (GPIO_BANK67_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK23_DIR       *(unsigned int*)(GPIO_BANK23_BASE)
#define GPIO_BANK23_DAT       *(unsigned int*)(GPIO_BANK23_BASE + GPIO_DAT_OFFSET)
#define GPIO_BANK23_SET       *(unsigned int*)(GPIO_BANK23_BASE + GPIO_SET_OFFSET)
#define GPIO_BANK23_CLR       *(unsigned int*)(GPIO_BANK23_BASE + GPIO_CLR_OFFSET)

/*System MMR Declaration*/
#define SYS_BASE           0x01C14000
#define HOST0CFG           *(unsigned int*)(SYS_BASE + 0x040)  //ARM HOST0CFG
#define KICK0R             *(unsigned int*)(SYS_BASE + 0x038)
#define KICK1R             *(unsigned int*)(SYS_BASE + 0x03c)
#define PINMUX0            *(unsigned int*)(SYS_BASE + 0x120)  //PINMUX0
#define PINMUX1            *(unsigned int*)(SYS_BASE + 0x124)  //PINMUX1
#define PINMUX2            *(unsigned int*)(SYS_BASE + 0x128)  //PINMUX2
#define PINMUX3            *(unsigned int*)(SYS_BASE + 0x12C)  //PINMUX3
#define PINMUX4            *(unsigned int*)(SYS_BASE + 0x130)  //PINMUX4
#define PINMUX5            *(unsigned int*)(SYS_BASE + 0x134)  //PINMUX5
#define PINMUX6            *(unsigned int*)(SYS_BASE + 0x138)  //PINMUX6
#define PINMUX7            *(unsigned int*)(SYS_BASE + 0x13C)  //PINMUX7
#define PINMUX8            *(unsigned int*)(SYS_BASE + 0x140)  //PINMUX8
#define PINMUX9            *(unsigned int*)(SYS_BASE + 0x144)  //PINMUX9
#define PINMUX10           *(unsigned int*)(SYS_BASE + 0x148)  //PINMUX10
#define PINMUX11           *(unsigned int*)(SYS_BASE + 0x14C)  //PINMUX11
#define PINMUX12           *(unsigned int*)(SYS_BASE + 0x150)  //PINMUX12
#define PINMUX13           *(unsigned int*)(SYS_BASE + 0x154)  //PINMUX13
#define PINMUX14           *(unsigned int*)(SYS_BASE + 0x158)  //PINMUX14
#define PINMUX15           *(unsigned int*)(SYS_BASE + 0x15C)  //PINMUX15
#define PINMUX16           *(unsigned int*)(SYS_BASE + 0x160)  //PINMUX16
#define PINMUX17           *(unsigned int*)(SYS_BASE + 0x164)  //PINMUX17
#define PINMUX18           *(unsigned int*)(SYS_BASE + 0x168)  //PINMUX18
#define PINMUX19           *(unsigned int*)(SYS_BASE + 0x16C)  //PINMUX19
#define CFGCHIP0           *(unsigned int*)(SYS_BASE + 0x17C)
#define CFGCHIP2           *(unsigned int*)(SYS_BASE + 0x184)
#define CFGCHIP3           *(unsigned int*)(SYS_BASE + 0x188)
#define PD0                0   /*Power Domain-0*/
#define PD1                1   /*Power Domain-1*/

#define PLLEN_MUX_SWITCH         4
#define PLL_LOCK_TIME_CNT        2400
#define PLL_STABILIZATION_TIME   2000
#define PLL_RESET_TIME_CNT       200

OnTargetConnect( )
{
    GEL_Trace(0);
    Clear_Memory_Map();
    Setup_Memory_Map();

    setup_ST4_PSC();

    setup_mDDR();
}

menuitem "ST4"

hotmenu TestStartup()
{
  GEL_Trace(2);
  setup_ST4_PSC();
  setup_mDDR();
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Clear_Memory_Map( )                                                     *
 *      Clear the Memory Map                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu Clear_Memory_Map()
{
    GEL_MapOff( );
    GEL_MapReset( );
    GEL_TextOut("\tMemory Map Cleared.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu Setup_Memory_Map()
{
    GEL_MapOn( );
    GEL_MapReset( );

    /* ARM */
    GEL_MapAddStr( 0xFFFD0000, 0, 0x00010000, "R|W|AS4", 0 );   // ARM Local ROM
    GEL_MapAddStr( 0xFFFE0000, 0, 0x00002000, "R|W|AS4", 0 );   // ARM INTC
    GEL_MapAddStr( 0xFFFF0000, 0, 0x00002000, "R|W|AS4", 0 );   // ARM Local RAM
    GEL_MapAddStr( 0x01BC0000, 0, 0x00001000, "R|W|AS4", 0 );   // ARM ETB Memory
    GEL_MapAddStr( 0x01BC1000, 0, 0x00000800, "R|W|AS4", 0 );   // ARM ETB Regs
    GEL_MapAddStr( 0x01BC1800, 0, 0x00000100, "R|W|AS4", 0 );   // ARM Ice Crusher

    /* DSP */
    GEL_MapAddStr( 0x00700000, 0, 0x00100000, "R|W|AS4", 0 );   // DSP L2 ROM
    GEL_MapAddStr( 0x00800000, 0, 0x00040000, "R|W|AS4", 0 );   // DSP l2 RAM
    GEL_MapAddStr( 0x00E00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P RAM
    GEL_MapAddStr( 0x00F00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D RAM
    GEL_MapAddStr( 0x01800000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Interrupt Controller
    GEL_MapAddStr( 0x01810000, 0, 0x00001000, "R|W|AS4", 0 );   // DSP Powerdown Controller
    GEL_MapAddStr( 0x01811000, 0, 0x00001000, "R|W|AS4", 0 );   // DSP Security ID
    GEL_MapAddStr( 0x01812000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP Revision ID
    GEL_MapAddStr( 0x01820000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP EMC
    GEL_MapAddStr( 0x01830000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Internal Reserved
    GEL_MapAddStr( 0x01840000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Memory System

    GEL_MapAddStr( 0x11700000, 0, 0x00100000, "R|W|AS4", 0 );   // DSP L2 ROM (mirror)
    GEL_MapAddStr( 0x11800000, 0, 0x00040000, "R|W|AS4", 0 );   // DSP l2 RAM (mirror)
    GEL_MapAddStr( 0x11E00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P RAM (mirror)
    GEL_MapAddStr( 0x11F00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D RAM (mirror)
 
    /* Shared RAM */
    GEL_MapAddStr( 0x80000000, 0, 0x00020000, "R|W|AS4", 0 );   // Shared RAM

    /* EMIFA */
    GEL_MapAddStr( 0x40000000, 0, 0x20000000, "R|W|AS4", 0 );   // EMIFA SDRAM Data
    GEL_MapAddStr( 0x60000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS2
    GEL_MapAddStr( 0x62000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS3
    GEL_MapAddStr( 0x64000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS4
    GEL_MapAddStr( 0x66000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS5
    GEL_MapAddStr( 0x68000000, 0, 0x00008000, "R|W|AS4", 0 );   // EMIFA Control

    /* DDR */
    GEL_MapAddStr( 0xB0000000, 0, 0x00008000, "R|W|AS4", 0 );   // DDR Control
    GEL_MapAddStr( 0xC0000000, 0, 0x20000000, "R|W|AS4", 0 );   // DDR Data

    /* Peripherals */
    GEL_MapAddStr( 0x01C00000, 0, 0x00008000, "R|W|AS4", 0 );   // TPCC0
    GEL_MapAddStr( 0x01C08000, 0, 0x00000400, "R|W|AS4", 0 );   // TPTC0
    GEL_MapAddStr( 0x01C08400, 0, 0x00000400, "R|W|AS4", 0 );   // TPTC1
    GEL_MapAddStr( 0x01C10000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC 0
    GEL_MapAddStr( 0x01C11000, 0, 0x00001000, "R|W|AS4", 0 );   // PLL Controller 0
    GEL_MapAddStr( 0x01C12000, 0, 0x00001000, "R|W|AS4", 0 );   // Key Manager
    GEL_MapAddStr( 0x01C13000, 0, 0x00001000, "R|W|AS4", 0 );   // Security Controller
    GEL_MapAddStr( 0x01C14000, 0, 0x00001000, "R|W|AS4", 0 );   // BootConfig
    GEL_MapAddStr( 0x01C16000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 0
    GEL_MapAddStr( 0x01C17000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 2
    GEL_MapAddStr( 0x01C20000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 0
    GEL_MapAddStr( 0x01C21000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 1
    GEL_MapAddStr( 0x01C22000, 0, 0x00001000, "R|W|AS4", 0 );   // I2C 0
    GEL_MapAddStr( 0x01C23000, 0, 0x00001000, "R|W|AS4", 0 );   // RTC
    GEL_MapAddStr( 0x01C24000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 1
    GEL_MapAddStr( 0x01C30000, 0, 0x00000200, "R|W|AS4", 0 );   // dMax Data RAM 0
    GEL_MapAddStr( 0x01C32000, 0, 0x00000200, "R|W|AS4", 0 );   // dMax Data RAM 1
    GEL_MapAddStr( 0x01C34000, 0, 0x00004000, "R|W|AS4", 0 );   // dMax Control Registers
    GEL_MapAddStr( 0x01C38000, 0, 0x00001000, "R|W|AS4", 0 );   // dMAX MAX0 Config Memory
    GEL_MapAddStr( 0x01C3C000, 0, 0x00001000, "R|W|AS4", 0 );   // dMAX MAX1 Config Memory
    GEL_MapAddStr( 0x01C40000, 0, 0x00001000, "R|W|AS4", 0 );   // MMC/SD 0
    GEL_MapAddStr( 0x01C41000, 0, 0x00001000, "R|W|AS4", 0 );   // SPI 0
    GEL_MapAddStr( 0x01C42000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 0
    GEL_MapAddStr( 0x01C43000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 0
    GEL_MapAddStr( 0x01D00000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 Control
    GEL_MapAddStr( 0x01D01000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 FIFO Ctrl
    GEL_MapAddStr( 0x01D02000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 Data
    GEL_MapAddStr( 0x01D0C000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 1
    GEL_MapAddStr( 0x01D0D000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 2
    GEL_MapAddStr( 0x01D0E000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 4
    GEL_MapAddStr( 0x01D10000, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP 0 Control
    GEL_MapAddStr( 0x01D10800, 0, 0x00000200, "R|W|AS4", 0 );   // McBSP 0 FIFO Ctrl
    GEL_MapAddStr( 0x01D11000, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP 1 Control
    GEL_MapAddStr( 0x01D11800, 0, 0x00000200, "R|W|AS4", 0 );   // McBSP 1 FIFO Ctrl
    GEL_MapAddStr( 0x01E00000, 0, 0x00010000, "R|W|AS4", 0 );   // USB0 (USB HS) Cfg
    GEL_MapAddStr( 0x01E10000, 0, 0x00001000, "R|W|AS4", 0 );   // UHPI Cfg
    GEL_MapAddStr( 0x01E11000, 0, 0x00001000, "R|W|AS4", 0 );   // UHPI (IODFT)
    GEL_MapAddStr( 0x01E13000, 0, 0x00001000, "R|W|AS4", 0 );   // LCD Controller
    GEL_MapAddStr( 0x01E14000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 1
    GEL_MapAddStr( 0x01E15000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 2
    GEL_MapAddStr( 0x01E16000, 0, 0x00001000, "R|W|AS4", 0 );   // UPP
    GEL_MapAddStr( 0x01E17000, 0, 0x00001000, "R|W|AS4", 0 );   // VPIF
    GEL_MapAddStr( 0x01E18000, 0, 0x00002000, "R|W|AS4", 0 );   // SATA
    GEL_MapAddStr( 0x01E1A000, 0, 0x00001000, "R|W|AS4", 0 );   // PLL Controller 1
    GEL_MapAddStr( 0x01E1B000, 0, 0x00001000, "R|W|AS4", 0 );   // MMC/SD 1
    GEL_MapAddStr( 0x01E20000, 0, 0x00002000, "R|W|AS4", 0 );   // EMAC CPPI port
    GEL_MapAddStr( 0x01E22000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC CPGMACSS registers
    GEL_MapAddStr( 0x01E23000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC CPGMAC registers
    GEL_MapAddStr( 0x01E24000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC MDIO port
    GEL_MapAddStr( 0x01E25000, 0, 0x00001000, "R|W|AS4", 0 );   // USB1 (USB FS)
    GEL_MapAddStr( 0x01E26000, 0, 0x00001000, "R|W|AS4", 0 );   // GPIO
    GEL_MapAddStr( 0x01E27000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC 1
    GEL_MapAddStr( 0x01E28000, 0, 0x00001000, "R|W|AS4", 0 );   // I2C 1
    GEL_MapAddStr( 0x01E29000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 3
    GEL_MapAddStr( 0x01E2A000, 0, 0x00001000, "R|W|AS4", 0 );   // PBIST Controller
    GEL_MapAddStr( 0x01E2B000, 0, 0x00001000, "R|W|AS4", 0 );   // PBIST Combiner
    GEL_MapAddStr( 0x01E2C000, 0, 0x00001000, "R|W|AS4", 0 );   // System Config

    GEL_MapAddStr( 0x01E30000, 0, 0x00008000, "R|W|AS4", 0 );   // TPCC1
    GEL_MapAddStr( 0x01E38000, 0, 0x00000400, "R|W|AS4", 0 );   // TPTC2
    GEL_MapAddStr( 0x01F00000, 0, 0x00001000, "R|W|AS4", 0 );   // EPWM 0
    GEL_MapAddStr( 0x01F01000, 0, 0x00001000, "R|W|AS4", 0 );   // HRPWM 0
    GEL_MapAddStr( 0x01F02000, 0, 0x00001000, "R|W|AS4", 0 );   // EPWM 1
    GEL_MapAddStr( 0x01F03000, 0, 0x00001000, "R|W|AS4", 0 );   // HRPWM 1
    GEL_MapAddStr( 0x01F06000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 0
    GEL_MapAddStr( 0x01F07000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 1
    GEL_MapAddStr( 0x01F08000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 2
    GEL_MapAddStr( 0x01F0B000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 5
    GEL_MapAddStr( 0x01F0C000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 2
    GEL_MapAddStr( 0x01F0D000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 3
    GEL_MapAddStr( 0x01F0E000, 0, 0x00001000, "R|W|AS4", 0 );   // SPI1
    GEL_MapAddStr( 0x01F10000, 0, 0x00001000, "R|W|AS4", 0 );   // McBSP 0 FIFO Data
    GEL_MapAddStr( 0x01F11000, 0, 0x00001000, "R|W|AS4", 0 );   // McBSP 1 FIFO Data
    GEL_TextOut("\tMemory Map Setup Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu setup_mDDR()
{
  GEL_TextOut("\tSetting up ST4 mDDR...\n","Output",1,1,1);

  /* values copied from AISgen setup */

  /* ... should result in a 405MHz CPU, 33.75MHz SDRAM, 45MHz EMAC */
  device_PLL0(0, 2, 30, 1, 1, 2, 12, 9);

  /* ... and 297MHz mDDR */
  device_PLL1(22,2,1,2,6);
  DEVICE_mDDRConfig(297);

  GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

/**************************************************************************************************************************************************
   Device_PLL0 init:

   CLKMODE -  0---->On Chip Oscilator  1---->External Oscilator
   PLL0_SYSCLK1 - Not used on Freon subchip, fixed divider (/1) - allow to change div1
   PLL0_SYSCLK2 - Used on Freon subchip, but it has a fixed divider ratio to SYSCLK1(/2) - should be used for sc ASYNC3 domain
                  to simplify clock management for peripherals during the ROM boot loader CFGCHIP3[ASYNC3_CLKSRC] - configure with div1
   PLL0_SYSCLK3 - Variable Divider, not used on Freon subchip, but ASYNC1 (EMIFA) on matrix - treat same as in Primus (configure)
   PLL0_SYSCLK4 - Used on Freon subchip, but it has a fixed ratio to div1 (/4) - configure with div1
   PLL0_SYSCLK5 - Variable divider, not used on Freon subchip - do nothing
   PLL0_SYSCLK6 - Not used on Freon subchip, fixed ratio to div1 (/1) - configure with div1
   PLL0_SYSCLK7 - Variable divider, is used on Freon subchip (Test, RMII, possibly USB 1.1) - treat the same as on Primus (configure)
   PLL0_SYSCLK8 - Variable divider, not used on Freon subchip - treat same as in Primus (do nothing)
   PLL0_SYSCLK9 - Variable divider, used on Freon subchip (test) - treat same as in Primus (do nothing)
   DIV4p5CLOCK  - Not used on Freon, can be used in in EMIFA on matrix - treat same as in Primus - configure in EMIF setups, not here
******************************************************************************************************************************************************/
device_PLL0(unsigned int CLKMODE, unsigned int PREDIV, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

   unsigned int i=0;

   /* Clear PLL lock bit */
   CFGCHIP0 &= ~(0x00000010);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   PLL0_PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   PLL0_PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   PLL0_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
   PLL0_PLLCTL &= 0xFFFFFEFF;
   PLL0_PLLCTL |= (CLKMODE << 8);

   /*Clear PLLRST bit to reset the PLL */
   PLL0_PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   PLL0_PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   PLL0_PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   PLL0_PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

   /*Program the required multiplier value in PLLM*/
   PLL0_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /* Prediv setup -Not required */
   PLL0_PREDIV = 0x8000 | PREDIV; /* Make POSTDIV as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL0_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   PLL0_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
   PLL0_PLLDIV2 = 0x8000 | PLLDIV2;
   PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1);
   PLL0_PLLDIV6 = 0x8000 | PLLDIV1;
   PLL0_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
   PLL0_PLLDIV7 = 0x8000 | PLLDIV7;   /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/


   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   PLL0_PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while(PLL0_PLLSTAT & 0x1==1) { }

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
   for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL0_PLLCTL |= 0x8;

   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL0_PLLCTL |=  0x1;

   /* SET PLL lock bit*/
   CFGCHIP0 |= (0x1 << 4) & 0x00000010;
}


/**********************************************************************************
DDR PLL1 init:

***********************************************************************************/

device_PLL1(unsigned int PLLM,unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3 ) {

   unsigned int i=0;

   /* Clear PLL lock bit */
   CFGCHIP3 &= ~(0x00000020);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   PLL1_PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   PLL1_PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   PLL1_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
   /* PLL1_PLLCTL &= 0xFFFFFEFF;
   PLL1_PLLCTL |= (CLKMODE << 8); */

   /*Clear PLLRST bit to reset the PLL */
   PLL1_PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   PLL1_PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   PLL1_PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   PLL1_PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

   /*Program the required multiplier value in PLLM*/
   PLL1_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL1_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL1_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   PLL1_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
   PLL1_PLLDIV2 = 0x8000 | PLLDIV2;   /* Make PLLDIV2 as bootpacket, do it for other PLLDIVx to if required*/
   PLL1_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/

   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   PLL1_PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while(PLL1_PLLSTAT & 0x1==1) { }

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - */
   for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL1_PLLCTL |= 0x8;

   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL1_PLLCTL |=  0x1;

   /* SET PLL lock bit*/
   CFGCHIP3 |= (0x1 << 5) & 0x00000020;

}

/**********************************************************************************
Device Kick Unlock:
    Kick0 register + data (unlock)
    Kick1 register + data (unlock)
***********************************************************************************/
hotmenu DEVICE_kickUnlock() {
   KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
   KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock)
 }


/**********************************************************************************
  PSC Common functions :

***********************************************************************************/
/*Force module state without handshaking */
PSC1_LPSC_force(unsigned int LPSC_num) {
    *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) | 0x80000000);
}

/*SyncReset Function for PSC1*/
PSC1_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x1 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0001;
      PSC1_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x1);
    }
}

/*Enable Function for PSC1*/
PSC1_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC1_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
    }
}

/*LPSC Enable Function for ARM or DSP*/
PSC0_LPSC_enableCore(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x11F) != 0x103 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFEE0) | 0x0103;
      PSC0_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x11F) !=0x103);
    }
}

/*SyncReset Function for PSC0*/
PSC0_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x1 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0001;
      PSC0_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x1);
    }
}

/*Enable Function for PSC0*/
PSC0_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC0_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
    }
}

hotmenu setup_ST4_PSC()
{
    GEL_TextOut("\tEnabling minimal ST4 PSCs...\n","Output",1,1,1);

    // PSC0
    PSC0_LPSC_enable(0, LPSC_EDMA_CC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC1);
    PSC0_LPSC_enable(0, LPSC_EMIFA);
    PSC0_LPSC_enable(0, LPSC_SPI0);
    PSC0_LPSC_enable(0, LPSC_MMCSD0);
    PSC0_LPSC_enable(0, LPSC_ARM_AINTC);
    PSC0_LPSC_enable(0, LPSC_ARM_RAMROM);
    PSC0_LPSC_enable(0, LPSC_UART0);
    PSC0_LPSC_enable(0, LPSC_SCR0);
    PSC0_LPSC_enable(0, LPSC_SCR1);
    PSC0_LPSC_enable(0, LPSC_SCR2);
    //PSC0_LPSC_enable(0, LPSC_ARM);
    //PSC0_LPSC_enable(1, LPSC_DSP);

    // PSC1
    PSC1_LPSC_enable(0, LPSC_EDMA_CC1);
    //PSC1_LPSC_enable(0, LPSC_USB20);
    //PSC1_LPSC_enable(0, LPSC_USB11);
    PSC1_LPSC_enable(0, LPSC_GPIO);
    //PSC1_LPSC_enable(0, LPSC_UHPI);
    //PSC1_LPSC_enable(0, LPSC_EMAC);
    //PSC1_LPSC_enable(0, LPSC_DDR);
    PSC1_LPSC_enable(0, LPSC_MCASP0);
    //PSC1_LPSC_force(LPSC_SATA);
    //PSC1_LPSC_enable(0, LPSC_SATA);
    PSC1_LPSC_enable(0, LPSC_VPIF);
    PSC1_LPSC_enable(0, LPSC_SPI1);
    PSC1_LPSC_enable(0, LPSC_I2C1);
    PSC1_LPSC_enable(0, LPSC_UART1);
    PSC1_LPSC_enable(0, LPSC_UART2);
    PSC1_LPSC_enable(0, LPSC_MCBSP0);
    PSC1_LPSC_enable(0, LPSC_MCBSP1);
    PSC1_LPSC_enable(0, LPSC_LCDC);
    PSC1_LPSC_enable(0, LPSC_EPWM);
    PSC1_LPSC_enable(0, LPSC_MMCSD1);
    PSC1_LPSC_enable(0, LPSC_UPP);
    //PSC1_LPSC_enable(0, LPSC_ECAP);
    PSC1_LPSC_enable(0, LPSC_EDMA_TC2);
    //PSC1_LPSC_enable(0, LPSC_SCR_F0);
    //PSC1_LPSC_enable(0, LPSC_SCR_F1);
    //PSC1_LPSC_enable(0, LPSC_SCR_F2);
    //PSC1_LPSC_enable(0, LPSC_SCR_F6);
    //PSC1_LPSC_enable(0, LPSC_SCR_F7);
    //PSC1_LPSC_enable(0, LPSC_SCR_F8);
    //PSC1_LPSC_enable(0, LPSC_BR_F7);
    PSC1_LPSC_enable(0, LPSC_SHARED_RAM);

    GEL_TextOut("\tPSC Enable Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
    GEL_TextOut("\tPSC Enable Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

DEVICE_mDDRConfig(unsigned int freq)
{
    /*Enable the Clock to EMIF3A SDRAM*/
    PSC1_LPSC_enable(PD0, LPSC_DDR);

    /*If VTP claiberation enabled , then skip the VTP calibration*/
    if((VTPIO_CTL & 0x00000040))
    {
       // Begin VTP Calibration
       VTPIO_CTL |= (0x00004000);     // Set IOPWRDN bit to enable input buffer powerdown enable mode
       VTPIO_CTL &= ~(0x00000040);    // Clear POWERDN bit (enable VTP)

       // Pulse (low) CLRZ to initiate VTP IO Calibration
       VTPIO_CTL |= (0x00002000);     // Set CLRZ bit
       VTPIO_CTL &= ~(0x00002000);    // Clear CLRZ bit (CLRZ should be low for at least 2ns)
       VTPIO_CTL |= 0x00002000;       // Set CLRZ bit

       // Polling READY bit to see when VTP calibration is done
       while(!((VTPIO_CTL & 0x00008000)>>15)) {}

       VTPIO_CTL |= 0x00000080;       // Set LOCK bit for static mode
       VTPIO_CTL |= 0x00000100;       // Set PWRSAVE bit to save power
       VTPIO_CTL |= 0x00000040;       // Set POWERDN bit to power down VTP module
       // End VTP Calibration
    }

    EMIF3A_SDCR |= 0x00800000; // Set BOOTUNLOCK

    // **********************************************************************************************
    // Setting based on 512Mb mDDR MT46H32M16LFBF-6 on EVM
    // Config DDR timings
    DDRCTL      = (0x0               << 8)   |  // Reserved
                  (0x1               << 7)   |  // EXT_STRBEN
                  (0x1               << 6)   |  // PWRDNEN
                  (0x0               << 3)   |  // Reserved
                  (0x4               << 0);     // RL

    EMIF3A_SDCR = (EMIF3A_SDCR & 0xF0000000) |  // Reserved
                  (0x1               << 27)  |  // DDR2TERM1
                  (0x0               << 26)  |  // IBANK_POS
                  (0x1               << 25)  |  // MSDRAMEN
                  (0x0               << 24)  |  // DDRDRIVE1
                  (0x0               << 23)  |  // BOOTUNLOCK
                  (0x0               << 22)  |  // DDR2DDQS
                  (0x0               << 21)  |  // DDR2TERM0
                  (0x0               << 20)  |  // DDR2EN
                  (0x0               << 19)  |  // DDRDLL_DIS
                  (0x0               << 18)  |  // DDRDRIVE0
                  (0x1               << 17)  |  // DDREN
                  (0x1               << 16)  |  // SDRAMEN
                  (0x1               << 15)  |  // TIMUNLOCK
                  (0x1               << 14)  |  // NM
                  (0x0               << 12)  |  // Reserved
                  (0x3               << 9)   |  // CL
                  (0x0               << 7)   |  // Reserved
                  (0x2               << 4)   |  // IBANK
                  (0x0               << 3)   |  // Reserved
                  (0x2               << 0);     // PAGESIZE

    // Subtracting 0.5 instead of 1 so that the int is rounded up after truncating a real value
    EMIF3A_SDTIMR1 = (((unsigned int) ((97.5 * freq / 1000) - 0.5)) << 25) |  // tRFC
                     (((unsigned int) ((18.0 * freq / 1000) - 0.5)) << 22) |  // tRP
                     (((unsigned int) ((18.0 * freq / 1000) - 0.5)) << 19) |  // tRCD
                     (((unsigned int) ((15.0 * freq / 1000) - 0.5)) << 16) |  // tWR
                     (((unsigned int) ((42.0 * freq / 1000) - 0.5)) << 11) |  // tRAS
                     (((unsigned int) ((60.0 * freq / 1000) - 0.5)) << 6)  |  // tRC
                     (((unsigned int) ((12.0 * freq / 1000) - 0.5)) << 3)  |  // tRRD
                     (EMIF3A_SDTIMR1 & 0x4)                                |  // Reserved
                     (((unsigned int) ((2.0 * freq / 1000) - 0.5))  << 0);    // tWTR

    // Subtracting 0.5 instead of 1 so that the int is rounded up after truncating a real value
    // tRASMAX is rounded down so subtracting 1
    // CAS/CL = 3
    EMIF3A_SDTIMR2 = (EMIF3A_SDTIMR2 & 0x80000000)                           |  // Reserved
                     (((unsigned int) ((70000 / 7812.5) - 1))        << 27)  |  // tRASMAX [(70us/7.8125us)-1]
                     (0x0                                            << 25)  |  // tXP
                     (0x0                                            << 23)  |  // tODT (Not supported)
                     (((unsigned int) ((120.0 * freq / 1000) - 0.5)) << 16)  |  // tXSNR
                     ((200 - 1)                                      << 8)   |  // tXSRD (200 Cycles)
                     ((1 - 1)                                        << 5)   |  // tRTP (1 Cycle)
                     (0x0                                            << 0);     // tCKE
 

    EMIF3A_SDCR    &= ~0x00008000; // Clear TIMUNLOCK

    EMIF3A_SDCR2   = 0x00000000; // IBANK_POS set to 0 so this register does not apply
    EMIF3A_SDRCR   = (0x1                                          << 31)  |  // LPMODEN
                     (0x1                                          << 30)  |  // MCLKSTOPEN
                     (0x0                                          << 24)  |  // Reserved
                     (0x0                                          << 23)  |  // SR_PD
                     (0x0                                          << 16)  |  // Reserved
                     (((unsigned int) ((7.8125 * freq) + 0.5))     << 0);     // RR

    /*SyncReset the Clock to EMIF3A SDRAM*/
    PSC1_LPSC_SyncReset(PD0, LPSC_DDR);

    /*Enable the Clock to EMIF3A SDRAM*/
    PSC1_LPSC_enable(PD0, LPSC_DDR);

    EMIF3A_SDRCR &= ~0xC0000000;  // disable self-refresh
}

  • 0
    TI__Mastermind 30830 points

    I don't see in your GEL file where you are enabling the timers, nor routing a clock source to the timers.

    The attached GEL file is what we use to run our OMAPL138 regression tests with.

    Alan

    6253.OMAPL138_ARM.gel

    2350.OMAPL138_DSP.gel

  • 0 in reply to Alan DeMars
    Intellectual 810 points

    I'm sorry if I'm missing it, but I don't see where timers or clock source routing is happening in your GEL files either.  (In fact, it looks like my GEL files at one point started out as your GEL files).

    Your OnTargetConnect looks like,

    OnTargetConnect( )
    {
        Clear_Memory_Map();
        Setup_Memory_Map();

        /* You can choose to run this if you only have the experimenter kit        */
        /* It will not turn PSC on for the peripherals on the user interface board */
        /* But it does not hurt if you choose to run PSC_All_On_Full_EVM() even if */
        /* you only have the experimenter kit                                      */
        /* PSC_All_On_Experimenter(); */

        PSC_All_On_Full_EVM();
       
        Core_300MHz_mDDR_132MHz();
       
        Wake_DSP();
    }

    mine looks like,

    OnTargetConnect( )
    {
        GEL_Trace(0);
        Clear_Memory_Map();
        Setup_Memory_Map();

        setup_ST4_PSC();

        setup_mDDR();
    }

    which should do the exact same thing, but without waking the DSP.    My setup_ST4_PSC sets up PSC (just like PSC_All_On_Full_EVM, but with things I can't use on my board not enabled), my setup_mDDR sets up the PLL0 and PLL1 registers, just like the Core_300MHz_mDDR_132MHz routine, but for a 405MHz core and 297MHz DDR.  I see nothing in either GEL file relating to clocks or timers.  I have tried to use the PSC_All_on_Full_EVM to initialize my hardware, but I got the same results (perhaps my testing was off, though).   Is there a possibility that there is a PSC enable in there that I need to get clocks to work?

    So, is there some other obvious place to enable timers and route clock sources?  Is it something I should be doing in the .cfg (which is the stock mutex task example .cfg currently).

       Jay

     

     

     

  • 0 in reply to Jay Gowdy81418
    TI__Mastermind 30830 points

    Hmm.

    What code is running on the ARM?

    Here is a thread that may apply to you:

        https://e2e.ti.com/support/embedded/int-embedded_software/int-bios/f/123/t/130234.aspx?Redirected=true

    Alan

  • 0 in reply to Alan DeMars
    Intellectual 810 points

    The code that is running on the ARM is the code generated in CCS5 when you create the SYS/BIOS Task Mutex example program.  I've pasted them at the end of the message.

    When I try to follow your link, I get a "Group Not Found" message.

       Jay

    mutex.c:

    /*
     *  ======== mutex.c ========
     *  This example shows the use of two tasks and one semaphore to perform
     *  mutual exclusive data access.
     */

    #include <xdc/std.h>
    #include <xdc/runtime/System.h>

    #include <ti/sysbios/BIOS.h>
    #include <ti/sysbios/knl/Clock.h>
    #include <ti/sysbios/knl/Task.h>
    #include <ti/sysbios/knl/Semaphore.h>

    #include <xdc/cfg/global.h>

    Void task1(UArg arg0, UArg arg1);
    Void task2(UArg arg0, UArg arg1);

    Int resource = 0;
    Semaphore_Handle sem;
    Task_Handle tsk1;
    Task_Handle tsk2;

    Int finishCount = 0;

    /*
     *  ======== main ========
     */
    Void main()
    {
        Task_Params taskParams;
           
        /* Create a Semaphore object to be use as a resource lock */
        sem = Semaphore_create(1, NULL, NULL);

        /* Create two tasks that share a resource*/
        Task_Params_init(&taskParams);
        taskParams.priority = 1;
        tsk1 = Task_create (task1, &taskParams, NULL);
       
        Task_Params_init(&taskParams);
        taskParams.priority = 2;
        tsk2 = Task_create (task2, &taskParams, NULL);

        BIOS_start();
    }

    /*
     *  ======== task1 ========
     */
    Void task1(UArg arg0, UArg arg1)
    {
        UInt32 time;

        for (;;) {
            System_printf("Running task1 function\n");

            if (Semaphore_getCount(sem) == 0) {
                System_printf("Sem blocked in task1\n");
            }

            /* Get access to resource */
            Semaphore_pend(sem, BIOS_WAIT_FOREVER);

            /* do work by waiting for 2 system ticks to pass */
            time = Clock_getTicks();
            while (Clock_getTicks() <= (time + 1)) {
                ;
            }

            /* do work on locked resource */
            resource += 1;
            /* unlock resource */

            Semaphore_post(sem);

            Task_sleep(10);
        }
    }

    /*
     *  ======== task2 ========
     */
    Void task2(UArg arg0, UArg arg1)
    {
        for (;;) {
            System_printf("Running task2 function\n");

            if (Semaphore_getCount(sem) == 0) {
                System_printf("Sem blocked in task2\n");
            }

            /* Get access to resource */
            Semaphore_pend(sem, BIOS_WAIT_FOREVER);

            /* do work on locked resource */
            resource += 1;
            /* unlock resource */
           
            Semaphore_post(sem);
           
            Task_sleep(10);
           
            finishCount++;
            if (finishCount == 5) {
                System_printf("Calling BIOS_exit from task2\n");
                BIOS_exit(0);
            }
        }
    }

    -----
    mutex.cfg

    var Defaults = xdc.useModule('xdc.runtime.Defaults');
    var Diags = xdc.useModule('xdc.runtime.Diags');
    var Error = xdc.useModule('xdc.runtime.Error');
    var Log = xdc.useModule('xdc.runtime.Log');
    var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
    var Main = xdc.useModule('xdc.runtime.Main');
    var Memory = xdc.useModule('xdc.runtime.Memory')
    var SysMin = xdc.useModule('xdc.runtime.SysMin');
    var System = xdc.useModule('xdc.runtime.System');
    var Text = xdc.useModule('xdc.runtime.Text');

    var BIOS = xdc.useModule('ti.sysbios.BIOS');
    var Clock = xdc.useModule('ti.sysbios.knl.Clock');
    var Task = xdc.useModule('ti.sysbios.knl.Task');
    var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
    var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
    var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');

    /*
     * Program.argSize sets the size of the .args section.
     * The examples don't use command line args so argSize is set to 0.
     */
    Program.argSize = 0x0;

    /*
     * Uncomment this line to globally disable Asserts.
     * All modules inherit the default from the 'Defaults' module.  You
     * can override these defaults on a per-module basis using Module.common$.
     * Disabling Asserts will save code space and improve runtime performance.
    Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
     */

    /*
     * Uncomment this line to keep module names from being loaded on the target.
     * The module name strings are placed in the .const section. Setting this
     * parameter to false will save space in the .const section.  Error and
     * Assert messages will contain an "unknown module" prefix instead
     * of the actual module name.
    Defaults.common$.namedModule = false;
     */

    /*
     * Minimize exit handler array in System.  The System module includes
     * an array of functions that are registered with System_atexit() to be
     * called by System_exit().
     */
    System.maxAtexitHandlers = 4;      

    /*
     * Uncomment this line to disable the Error print function. 
     * We lose error information when this is disabled since the errors are
     * not printed.  Disabling the raiseHook will save some code space if
     * your app is not using System_printf() since the Error_print() function
     * calls System_printf().
    Error.raiseHook = null;
     */

    /*
     * Uncomment this line to keep Error, Assert, and Log strings from being
     * loaded on the target.  These strings are placed in the .const section.
     * Setting this parameter to false will save space in the .const section.
     * Error, Assert and Log message will print raw ids and args instead of
     * a formatted message.
    Text.isLoaded = false;
     */

    /*
     * Uncomment this line to disable the output of characters by SysMin
     * when the program exits.  SysMin writes characters to a circular buffer.
     * This buffer can be viewed using the SysMin Output view in ROV.
    SysMin.flushAtExit = false;
     */

    /*
     * The BIOS module will create the default heap for the system.
     * Specify the size of this default heap.
     */
    BIOS.heapSize = 0x2000;

    /* System stack size (used by ISRs and Swis) */
    Program.stack = 0x1000;

    /* Circular buffer size for System_printf() */
    SysMin.bufSize = 0x400;

    /*
     * Create and install logger for the whole system
     */
    var loggerBufParams = new LoggerBuf.Params();
    loggerBufParams.numEntries = 32;
    var logger0 = LoggerBuf.create(loggerBufParams);
    Defaults.common$.logger = logger0;
    Main.common$.diags_INFO = Diags.ALWAYS_ON;

    System.SupportProxy = SysMin;

  • 0 in reply to Jay Gowdy81418
    TI__Mastermind 30830 points

    "The code that is running on the ARM is the code generated in CCS5 when you create the SYS/BIOS Task Mutex example program."

    Doh!

    The referenced email thread suggests that some form of linux uboot has run on the ARM prior to CCS getting control of it.

    In that case, uboot was grabbing and configuring timer 0 in a way that made it not work for SYS/BIOS.

    You could try adding this to your config file and see if it helps:

        var Clock = xdc.useModule('ti.sysbios.knl.Clock');

       Clock.timerId = 3;

    This forces SYS/BIOS to use a different timer than timer 0.

    Alan

  • 0 in reply to Alan DeMars
    Intellectual 810 points

    That didn't do it.   Also, more more information,  as far as I know nothing runs before the ARM code to configure anything except a GEL file when in CCS and the ROM Bootloader when booting from flash.

    I dug around in the Clock documentation, and added the following to my .cfg because it seemed like a good guess.

      // Tell the Clock module that YOU are providing the periodic interrupt
      Clock.tickSource = Clock.TickSource_USER;

      // this example uses the ti.sysbios.timers.dmtimer.Timer module
      var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');

      // create a dmtimer config parameter object
      var timerParams = new Timer.Params();

      // make sure you set the period to 1000 us (1ms)
      timerParams.period = 1000;

      // custom dmtimer config parameters here...
      timerParams.twer.ovf_wup_ena = 1;

      // Create the timer.
      // This example uses timer id 3.
      // The timer interrupt handler must be set to 'Clock.tick'.
      Timer.create(3, Clock.tick, timerParams);

    but, I got the following build error,

    C:\ti\ccsv5\utils\bin\gmake -k all
    'Building file: ../mutex.cfg'
    'Invoking: XDCtools'
    "C:/ti/xdctools_3_23_01_43/xs" --xdcpath="C:/ti/bios_6_33_03_33/packages;C:/ti/biospsp_03_00_01_00/drivers;C:/ti/edma3_lld_02_11_04_01/packages;C:/ti/ipc_1_24_02_27/packages;C:/Workdir/Vision/Software/ST4/common/platform;" xdc.tools.configuro -o configPkg -t ti.targets.arm.elf.Arm9 -p ST4_ARM -r release -c "C:/ti/ccsv5/tools/compiler/tms470" --compileOptions "-g --optimize_with_debug" "../mutex.cfg"
    making package.mak (because of package.bld) ...
    generating interfaces for package configPkg (because package/package.xdc.inc is older than package.xdc) ...
    configuring mutex.xe9 from package/cfg/mutex_pe9.cfg ...
    Timer is not supported for the specified device (OMAPL138).
    TMS320CDM740
    js: "C:/ti/bios_6_33_03_33/packages/ti/sysbios/timers/dmtimer/Timer.xs", line 899: Error: Timers unsupported on device!
    "C:/Workdir/Vision/Software/ST4/sandbox/ARM_SysBIOS_examples/task/mutex.cfg", line 23
    "./package/cfg/mutex_pe9.cfg", line 196
    "./package/cfg/mutex_pe9.cfg", line 275
    "./package/cfg/mutex_pe9.cfg", line 183
    gmake.exe: *** [package/cfg/mutex_pe9.xdl] Error 1
    js: "C:/ti/xdctools_3_23_01_43/packages/xdc/tools/Cmdr.xs", line 51: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.
    gmake: Target `all' not remade because of errors.

    Now, I know that there are timers on the actual ARM hardware, because the bare metal ARM code I have sets up a timer interrupt by directly pounding on the relevant registers.   Am I going to have to use the bare metal timer code I have to set up a SYS/BIOS Hwi which I will fool the clock package into thinking is a timer?   

      Jay

     

     

  • 0 in reply to Jay Gowdy81418
    TI__Mastermind 30830 points

    This board uses the ti.sysbios.timers.timer64.Timer module rather than the dmtimer.Timer module.

    You can use the same script but point the Timer var to timer64.Timer:

      // Tell the Clock module that YOU are providing the periodic interrupt
      Clock.tickSource = Clock.TickSource_USER;

      // this example uses the ti.sysbios.timers.dmtimer.Timer module
      var Timer = xdc.useModule('ti.sysbios.timers.timer64.Timer');

      // create a dmtimer config parameter object
      var timerParams = new Timer.Params();

      // make sure you set the period to 1000 us (1ms)
      timerParams.period = 1000;

      // Create the timer.

      // This example uses timer id 3.
      // The timer interrupt handler must be set to 'Clock.tick'.
      Timer.create(3, Clock.tick, timerParams);

    But this should be equivalent to setting Clock.timerId = 3;

    Did you actually try using the gel file I sent?

    Alan

  • 0 in reply to Alan DeMars
    Intellectual 810 points

    Alan,

    This is somewhat embarrassing.  It looks like I did not have a "real" problem.   What I was seeing was that when I stepped through code Task_sleep hung forever, and Clock_getTicks always returned the same values.  This is not the behavior I am used to from my experience with the DSP side, and I thought it was a bug in SYS/BIOS.  BUT, when I finally on a whim let it free run, it appears that everything just worked (sleeps happened, ticks advanced, etc.).

    Sorry for my confusion.    I thought about it for a bit and realized that interrupts were being disabled when stepping, and I found the "Disable interrupts when source stepping" check box in the Generic Debugger Options (doh) and turned it off to get the behavior I expect as the default.

    With that, I went back to the original code (no timer Id change or user clock), and it just worked, even stepping through it.   I realize that interrupts are firing in the background while I am stepping, but that is acceptable for now, and at least I am aware of the issue and of how to turn it on and off.

    Thanks for your patience, and I promise to have a real problem next time.

        Jay

  • 0 in reply to Jay Gowdy81418
    TI__Mastermind 30830 points

    Whew!

    I'm glad it was pilot error. I was running out of theories...

    Alan