hi
This is described in the datasheet about MSI Interrupt Generation in EP Mode
1. Ensure that the MSI support has been enabled in the device.
2. Read the value of MSI Address Register in the local PCIe configuration space.
3. Read the value of MSI Data Register in the local PCIe configuration space.
4. Determine the number of MSI vectors allocated (and the number requested) to the device.
5. Depending upon the number of MSI interrupts allocated, issue a Memory Write transaction with
the address same as MSI Address Register and Data same as MSI Data Register. In the data,
the LSBs can be modified to reflect appropriate MSI event that needs to be notified to Root
Complex.
6. The Memory Write transaction can also be optionally routed through the outbound address
translation interface if the destination PCIe address is not directly accessible.
I haved completed one to four steps, but I don’t know how to do the fifth or sixth