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c6713 EMIF Interface to FPGA

anwar naseem
Prodigy 40 points

Hi, 

On my custom board , c6713 has SRAM on CE2 and a FPGA on CE0. I can easily read /write on the sram after setting the ce2 register with the read/write timings. But I am unable to read/write from the FPGA. ( FPGA is working as A Synchronous SRAM with Read Enable, Chip enable, Write Enable and Output enable pins)

Debugging shows that on Read request from DSP , FPGA goes into the reading mode. But the data get by DSP is always 0.

Any suggestions , how to configure emif to communicate with FPGA.

Regards,

Anwar Naseem

 

  • 0
    TI__Guru* 84110 points

    Anwar,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    I am not sure what you mean by "A Synchronous SRAM". The most common method is for the FPGA to work as an asynchronous SRAM so that it operates exactly the same as the SRAM on CE2. If that is the case, then use the same settings as you use on CE2. For debugging, you may want to increase all of the read and write setup/strobe/hold timings to their maximum values, then tune them to more efficient values later.

    This is a combination of hardware and software since you may have signals connected incorrectly on your new board or you may have the EMIF register settings incorrect in the DSP or you may have teh FPGA programmed incorrectly.

    I would start by looking at the EMIF signals with an oscilliscope while running the DSP in a read loop. See what the address and control and data lines are doing, and compare those to the waveforms you see in the EMIF documentation.

    Regards,
    RandyP

  • 0
    Guru 26430 points

    It might be that the FPGA is removing the data from the bus too quickly. Maybe try changing the FPGA code to leave the data on the bus until the next transaction.

  • 0 in reply to Norman Wong
    Prodigy 40 points

    I have checked that fpga leaves the data on data bus till next read cycle via simulation.

    -Anwar

  • 0 in reply to anwar naseem
    Guru 26430 points

    Not much more to check. Sounds like the memory control lines are properly pinmuxed out. Maybe check the pinmux for the data lines. That's all I got.