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AM335 set gpio high in u-boot

ed mcnicholas
Intellectual 290 points

I am currently working off a custom board with 2 3.3v regulators that are by default off but in the current sdk version of uboot and the linux kernel continually reboot if the ethernet chipset which is powered by one of these regulators is not enabled.  What i am trying to do is enable gpio pins 1_22 and 1_23 in the uboot kernel.  Currently i have enabled the clock domain in pll.c and created a mux to place the 2 pins in mode 7 in mux.c.  I have then added an 3v3reg init function in evm.c which inits the pin mux and then i write to address GPIO1_BASE + OMAP_GPIO_OE to set the output enables for the 2 pins to 0 and then GPIO1_BASE+OMAP_GPIO_SETDATAOUT for the 2 pins to 1.  When i read back the register values they are correct but the lines are not high so i am going to assum i am missing something.  Any help would be greatly apreciated.

Thanks

Ed

  • 0
    Prodigy 110 points

    Hi, I have the same issue with another pins. I will come back when I find solution. Regards

  • 0 in reply to Patrick GAMBIER
    Prodigy 110 points

    Here is what I added in U-boot from TI. It runs. It is how to set GPIO3_7 as output.

    /* In mux.c file */

    static struct module_pin_mux gpio_pin_mux[] = {
     {OFFSET(emu0),      (MODE(7))},    /* GPIO3_7 */
     {-1},
    };

    static struct evm_pin_mux myboard_pin_mux[] = {
     {uart0_pin_mux,  PROFILE_ALL, DEV_ON_BASEBOARD},
     {i2c0_pin_mux,   PROFILE_ALL, DEV_ON_BASEBOARD},
     {nand_pin_mux,   PROFILE_ALL, DEV_ON_BASEBOARD},
     {rmii1_pin_mux,  PROFILE_ALL, DEV_ON_BASEBOARD},
     {mmc0_pin_mux,   PROFILE_ALL, DEV_ON_BASEBOARD},
     {spi0_pin_mux,   PROFILE_ALL, DEV_ON_BASEBOARD},
     {gpio_pin_mux,   PROFILE_ALL, DEV_ON_BASEBOARD},
     {0},
    };

    /* In my_application.c file */

    #define GPIO_OE   0x134 /* Output enable */
    #define GPIO_DATAIN  0x138 /* Input value */
    #define GPIO_DATAOUT  0x13C /* Write value */
    #define GPIO_CLEARDATAOUT 0x190 /* Set to 0 an output */
    #define GPIO_SETDATAOUT  0x194 /* Set to 1 an output */

    #define AM335X_CM_PER_GPIO1_CLKCTRL (0x44E00000+0xAC)
    #define AM335X_CM_PER_GPIO2_CLKCTRL (0x44E00000+0xB0)
    #define AM335X_CM_PER_GPIO3_CLKCTRL (0x44E00000+0xB4)

    #define AM335X_GPIO0_BASE 0x44E07000
    #define AM335X_GPIO1_BASE 0x4804C000
    #define AM335X_GPIO2_BASE 0x481AC000
    #define AM335X_GPIO3_BASE 0x481AE000

    #define GPIO0(value,offset) __raw_writel(value,(AM335X_GPIO0_BASE+offset));
    #define GPIO1(value,offset) __raw_writel(value,(AM335X_GPIO1_BASE+offset));
    #define GPIO2(value,offset) __raw_writel(value,(AM335X_GPIO2_BASE+offset));
    #define GPIO3(value,offset) __raw_writel(value,(AM335X_GPIO3_BASE+offset));

     /* Allows GPIO modules */
     __raw_writel(0x00000002,AM335X_CM_PER_GPIO1_CLKCTRL);
     __raw_writel(0x00000002,AM335X_CM_PER_GPIO2_CLKCTRL);
     __raw_writel(0x00000002,AM335X_CM_PER_GPIO3_CLKCTRL);

     /* Set GPIO3_7 as output */
     GPIO3(0xFFFFFFFF & ~0x80,GPIO_OE);

     /* GPIO3_7 to 1 */
     GPIO3(0x00000080,GPIO_SETDATAOUT);
     udelay(500000);
     /* GPIO3_7 to 0 */
     GPIO3(0x00000080,GPIO_CLEARDATAOUT);