I am planning a system using the DM814x parts. Of primary concern is the limitations on access from DSP to DDR memory. In the TRM on pages 174-175 the table shows the only interface from DSP (DSP/EDMA MMU) to the DDR (EDMA DMM) is thru EDMA DMM Tiler/Lisa1. This is also the path for HDVPSS Mstr1.
Does this mean that the DSP will be in conflict with the HDVPSS Mstr1 if we are streaming video? What is the impact of this on performance of the DSP and Video input?
Eric