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DM814x DSP to DDR limits

I am planning a system using the DM814x parts.  Of primary concern is the limitations on access from DSP to DDR memory.  In the TRM on pages 174-175 the table shows the only interface from DSP (DSP/EDMA MMU) to the DDR (EDMA DMM) is thru EDMA DMM Tiler/Lisa1.  This is also the path for HDVPSS Mstr1. 

Does this mean that the DSP will be in conflict with the HDVPSS Mstr1 if we are streaming video?  What is the impact of this on performance of the DSP and Video input?

Eric

  • The table/graph is in the data sheet SPRS647C --not the TRM.  Sorry.

  • Eric,

    Even if the C674x had a separate port into the DMM, the multiple masters in the device will still have to share the DDR memory space and bandwidth.

    An important part of your system analysis will be to add up all of the memory transfer bandwidth requirements of the various parts of your application, and then see how that sum compares to the available bandwidth. If your total is over 50% of what the DDR can handle, then you will want to look more closely at potential issues.

    There are controls and tradeoffs that you can make to set priorities between the various masters. I am not an expert on those, but it involves setting the priority/pressure values, for example in the INIT_PRIORITY_0/1 registers.

    There will be some latency issues whenever two or more masters want to access the same resource. The streaming video will not require all of the available bandwidth, so the C674x will be able to share this resource. The streaming will be broken into lines or sets of macroblocks, so there will be spaces in the middle of a frame when the DSP will be able to slip in. Or with priority adjustments you can set it the other way around.

    Most designers make limited analysis of these parameters, then look more closely if there are issues. It is good that you are thinking about it now, and by knowing what knobs can be turned later, you will be ready if any issues come up.

    Regards,
    RandyP