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DM368 and UART1 clock problem.

John Anderson
Genius 5240 points

I'm running the DM368 with a base clock of 680MHz and PLL1CLK4 is at 170MHZ.  My problem is that the UART1 clock frequency is off.  We didn't notice it until trying to run at 115200 and got garbage.  The lower clocks are off but not by as much as will work.  Apparently the dividers are not calculated correctly or perhaps the clock freq is too high to divide properly.  Wondering how others tackled this problem if at all.  Perhaps I need to set a different divider for PLL1CLK4, but not sure how the ramifications will affect other clock dependent devices.

JohnA

  • 0
    Genius 5240 points

    Turns out that the UART1 clock freq is not off.  I thought that it was because I judged it based on the duration of the start bit.  After looking further into the whole waveform I see that the bits of the data have the correct duration, but the start bit does not.  I compared the waveform against UART0, and UART0 has the correct start bit duration.

    JohnA