AM3359 Industrial Communications Kit

Suhel,

I beleive the Ethercat image is small enough to boot into and run from on- chip RAM (booting from Spi Flash.)

If I look at the Sitara chip it only has 256KB of L2 cache - this is the only memory on-chip

If EtherCAT is run from a locked cache - that would mean the chip can do nothing but protocol...

But I know it can do other things as well

I am still thinking that the stack is executed from cache... Please correct me if this not true

Suhel,

The IDK and ICE both have external DRAM. So, you could certainly use external memory.

We have two ways of doing EtherCAT

1. For simple applications, we can reduce system cost by not requiring external DRAM and running application and stack both on the chip. The L2 cache helps in the sense that it enables us to extend on-chip memory instead of it acting only as a fast copy of other code.

2. For more complex applications, an external DRAM (DDR2/DDR3) can be used. There is no support for SDRAM on AM335x.

SPI flash can be used for boot source but it cannot be used as execute-in-place memory because SPI flash in AM335x is not random access memory.

Thanks,

Maneesh

Suhel Dhanani said:

If I look at the Sitara chip it only has 256KB of L2 cache - this is the only memory on-chip

Definitely wrong. There are two blocks of SRAM in addition. In total 127kB. This (+L1/L2 caches) is enough to run a full EtherCAT slave stack, minimum OS config and application code. PRU-ICSS has local memory too. You will be surprised what can be done with a bit of memory still. Don't compare with Linux or other HLOS with megabytes of overhead. Here we target slave applications which have a clear definition of features and functions like sensors and I/O devices.

Certainly we would like to get more memory on chip in future...

Regards.