Hello everybody,
we are using Timer P3 on the omapl138 in 32 Bit unchained mode with PLUS features enabled. P3 1/2 is used by the arm and P3 3/4 is used by the dsp. When accessing shared registers (TCR, INTCTLSTAT), only the upper or lower halves are accessed (16 Bit aligned addresses). The timer events are not used to generate arm or dsp CPU interrupts. Instead of we trigger some edma transfers with the two timer events. The edma transfers reload the timers, acknowledge the timer events in INTCTLSTAT and do some other stuff. Additionally P3 1/2 works in clock mode and toggles its associated output port. Our problem is as follows:
Signal edges on the output port of P3 1/2 are lost when the dsp/edma operate on the registers of P3 3/4 in parallel. When P3 3/4 is stopped everything works fine. But as soon the dsp/edma begin to start, stop, acknowledge P3 3/4, signal edges on the output port of the other timer are lost. The edma events of P3 1/2 are still generated correctly, only the port doesn't change its state some time. This happens once every few minutes.
Is there any interaction between the upper and lower timer?
Thanks and have a nice day