• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 97 subscribers
  • Views 301 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

64Bit Timer Plus on OMAPL138

Marc48067
Expert 2000 points
Other Parts Discussed in Thread: OMAPL138

Hello everybody,

we are using Timer P3 on the omapl138 in 32 Bit unchained mode with PLUS features enabled. P3 1/2 is used by the arm and P3 3/4 is used by the dsp. When accessing shared registers (TCR, INTCTLSTAT), only the upper or lower halves are accessed (16 Bit aligned addresses). The timer events are not used to generate arm or dsp CPU interrupts. Instead of we trigger some edma transfers with the two timer events. The edma transfers reload the timers, acknowledge the timer events in INTCTLSTAT and do some other stuff. Additionally P3 1/2 works in clock mode and toggles its associated output port. Our problem is as follows:

Signal edges on the output port of P3 1/2 are lost when the dsp/edma operate on the registers of P3 3/4 in parallel. When P3 3/4 is stopped everything works fine. But as soon the dsp/edma begin to start, stop, acknowledge P3 3/4, signal edges on the output port of the other timer are lost. The edma events of P3 1/2 are still generated correctly, only the port doesn't change its state some time. This happens once every few minutes.

Is there any interaction between the upper and lower timer?

Thanks and have a nice day

 

 

 

 

 

  • 0
    Expert 2000 points

    I had a closer look at the problem and realized the following. A write to TIM34 register of P3 from dsp side has impact on the timer output port of P3 1/2. Signal edges on output port of P3 1/2 are lost, e.g. the clock output is corrupted. P3 3/4 has no own output port on the omapl138! The timer P3 3/4 doesn't need to run to force this behaviour! It is sufficient to write to TIM34. If the frequency of writing to TIM34 is increased, the number of errors on the output port of P3 1/2 also increases. Writing to other registers of P3 3/4 has no impact on the output port of P3 1/2. You can check the behaviour described above with a simple test program.

    Waiting for your answers....Thanks....

    Marc

  • 0 in reply to Marc48067
    Expert 2000 points

    In the mean time I did a workaround to avoid the problem. Now the timer P3 3/4 is operating in read reset mode. When I want to reset TIM34 I just read out TIM34 and the timer resets itself internally. So no more writes to TIM34 are done. Reading out TIM34 has no influence on the output port of P3 1/2.

    But there is still no answer why writing to TIM34 has influence on the output port of P3 1/2???

    Any ideas?