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EMAC TX (EMAC[0]_GMTXCLK and EMAC[0]_TXEN) seems to be powered down

Bharath Bhat
Prodigy 20 points

Hi,

I have a custom board with DM8168. EMAC0 has been connected to a Marvell ethernet switch via GMII. I see that the RX works fine but the TX side seems to be powered down. I don't see any activity on EMAC[0]_GMTXCLK or EMAC[0]_TXEN pins. Is there a special register which needs to be set to power up the TX module ?

Also, the Technical Reference Manual for DM816x says

"Program the VDD3P3V_PWDN register in the System module to power up the CPGMAC I/O cells
   (see the device-specific data manual). There are separate controls for MII I/O pins and GMII I/O pins, which are powered down by default at system reset, to save power."

But I can't find this register anywhere,

Regards

Bharath

  • 0
    Prodigy 20 points

    May be this is the problem,

    Below is a section from the silicon errata: (http://www.ti.com/lit/er/sprz329b/sprz329b.pdf)


    Details: Although EMAC_TXCLK is specific to the 10/100Mbps clock, if it is not running, then the
    1-Gbps mode does not work.
    In Ethernet boot, when the board is powered on, the Ethernet PHY chip auto-negotiates
    and establishes a link at either 10/100/1000 Mbps speed. If the link is established at 1
    Gbps, the Ethernet boot does not work for PHY chips that do not provide the
    EMAC_TXCLK clock signal. According to the GMII specification, the EMAC_TXCLK
    signal is not required to be provided by the PHY for 1-Gbps mode of operation, hence
    some of the PHYs may not provide this clock. In these cases, the Ethernet boot fails.
    Workaround: Use the PHY chip that outputs the transmit clock to MAC (EMAC_TXCLK pin) (e.g.,
    ET1011C PHY).
    Ensure that the PHY does not auto-negotiate to 1 Gbps by default, until boot occurs. At
    a later stage, the second-level bootloader or OS driver can enable 1-Gbps mode in the
    PHY via MDIO and restart auto-negotiation to switch to gigabit mode. A PHY chip might
    provide an input pin to disable/enable 1-Gbps mode by default, which can be overridden
    by using MDIO register settings

    Regards

    Bharath