SRIO booting for C6678

Answers are below:

1. You will use secondary boot loader and it is explained in the same user guide. Please let me know if it is not clear.  We have a new release of the document now.

2. The example uses DirectIO.

3.  The ROM boot can do through DDR configuration table that you need to configure. But it is not functional in C6670. In either case the user need to do the DDR configuration as it depends upon what DDR you are using.

Thanks,

Arun.

Dear Arun,

Thanks for the reply.

Let's focus on item 1.  After reading the updated bootloader user guide, I think I still can not figure out what will be the required steps since the document is too rough and abstract.

Above all, my target is: Configure SRIO Lane Setup as 1x4 for booting.  While only 2 lance setup, 4x1 ports and 2x2 ports, are possible from boot pins.

The use guide highlights 3 tables: Boot Parameter Table, Boot Table, Boot Configuration Table.

Now my questions are listed as follows.

    1. In my understanding, Boot Configuration Table will be used to modify SRIO relating registers to change its lane setup.  Right?
        Where can I find the Boot Configuration Table since the guide never mentions how user can modify it?
        Or could you please give an example to do it? 

    2. As stated in 2.5.5: Romparse is used to append the boot parameter to boot table or a boot configuration table.
        There is no documents and sample projects for Romparse. 

    3. As you mentioned, I can use secondary bootlader.  Are you referring to IBL?
        IBL is never mentioned in the bootloader user guide, is it to say all the described procedures are for RBL, but not for IBL?

    4. In user guide, Secondary Stage Bootloader is under I2C bootloader. And it also mentions that boot modes can be extended, such as SRIO, SPI, etc.
        So, for my problem, how should I set my DIP switches: I2C boot or SRIO boot? 

    5. According to advisory 8 in silicon errata, 1st step of IBL is to fix PLL locking issue for silicon revision 1.0
        However for silicon revision 2.0, is IBL still entered before RBL for SRIO booting?
        Or can I remove EEPROM in my design with silicon 2.0 for SRIO booting?

    6. Must all kinds of boot image be in Boot Table format?
        It is said hex6x is used to generate boot table format.  
        Is the output of MAD utility for multicore boot image also in boot table format?
        It seems hex6x is not included in MAD utility. 

Thanks.

Boll

Hello together,

instead of Boll I want to boot the C6678 with a secondary boot with PCIe via I²C. I've also the same understanding problems as Boll as there's no clear example for this case and the Bootloader document is not detailed enough. Having tried and understood the PCIe-Boot- and I²C-Boot-Example and having read the Bootloader User Guide and other documents and threads, I'm not able to answer all questions like:

-How to modify the Boot Parameter Table and load it? Where has this table to be written exactly?
-the whole workflow of the RBL and IBL is not very clear: when starts the IBL to work? does the RBL or IBL reads the Boot Parameter table? and so on...
-where have additional Boot Configuration Tables to written? In the EEPROM or I²C-Nor for example?

Can somebody provide a detailed secondary stage boot example with creating and writing all necessary tables?

Best Regards,
Bernd

Can anyone help to explain?

Sorry for the delay.

You should use the boot parameter table. As you can see that each boot mode have a boot parameter table that can be modified and sent through the secondary i2c boot loader. Unfortunately we don't have a clear example. You can check the IBL booting to get thedetails as the IBL is loaded in the I2C whihc will inturn boot any primary boot after fixing the PLL errata.

Thanks,

Arun.

Hello,

instead of using a secondary stage boot with I²C, it is much easier to modify the IBL in the MCSDK in that way that all components works. In my example I had to change the subsystem id and subvendor id for PCIe boot and now everything works fine.

Maybe also for SRIO booting you can modify the IBL for your purpose.

Best Regards,
Bernd

Dear Arun and Bernd,

Thanks for your reply.

I think you two are describing the same thing: Boot Parameter Table.

Bernd, if I am not wrong, you are modifying "BOOT_PARAMS_PCIE_T      pcie;", defined in tiboot_c66x.h.

And I need to modify BOOT_PARAMS_RIO_T for my purpose.

However after reading ibl source code, I still can not figure out how to modify it.

Bernd, could you please detail how you make the modifications?

After making the modification in ibl, I just need to rebuild it according to ibl\doc\build_instructions.txt, and write the generated i2crom_0x51_c6678_le.bin into EEPROM.

It is enough, no further steps, am I right?

Boll

Hello Boll,

sorry for the delay due to holiday. I'm NOT modifying the "BOOT_PARAMS_PCIE_T pcie". When the IBL starts, you have several possibilities to change every setup (SRIO or PCIe). In my case I modified the method "iblPCIeWorkaround()" in c66xinit.c and set the Subsystem and Subvendor ID in this way:

DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_SUBSYSTEM_SUBVENDOR_ID), 0xXXXXXXXX);

So you have to look which settings for SRIO should be modified and set the appropriate registers while IBL is running. Then you can compile the IBL and download it to I²C, thats correct (no further steps required).

Best Regards,
Bernd

Bool,

Were able to solve this issue?

Thanks,

Arun.