• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 100 subscribers
  • Views 472 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP-L138 on chip memory questions

Jay Gowdy81418
Intellectual 810 points
Other Parts Discussed in Thread: OMAP-L138, SYSBIOS

I am developing with an OMAP-L138 and have been operating under the assumption that the 128K of on-chip memory available to the DSP at 0x80000000 is fast memory that is not cached through L2.

I have now demonstrated to myself that my assumption about the caching is incorrect:  this memory is cached through L2 so I have to be careful to invalidate it when filling it with EDMA.

I want to know if my other assumption is wrong: 

  • is this on-chip memory faster than normal DDR?
  • Is it as fast as the portion of L2 I don't use as cache?
  • If so, doesn't the L2 caching cause some inefficiencies (if the memory is as fast as L2, doesn't caching through L2 essentially make it half as fast as it otherwise could be, as we are transferring from the fast on-chip memory to the equally fast L2 memory?)
  • Using my SYS/BIOS 6.3.33 config file, is there a way to turn off L2 caching for this section of memory?   
  • Would that be a dumb idea (since it would probably turn off L1 caching as well, correct?)
  • Optimally, is there a way to turn off L2 caching while keeping L1 caching for this memory?  (I'd be shocked if there was.)

Thanks,

    Jay

  • 0
    TI__Expert 7155 points

    Jay,

    Here are my comments:

    • is this on-chip memory faster than normal DDR?

    All of the on-chip memory including the shared RAM should be able to be accessed  faster than external memory.

    • Is it as fast as the portion of L2 I don't use as cache?

    The L2 memory is faster. The DSP does not need to go through the SCR to access L2 as it does to access the shared RAM (a.k.a. L3 RAM).

    • If so, doesn't the L2 caching cause some inefficiencies (if the memory is as fast as L2, doesn't caching through L2 essentially make it half as fast as it otherwise could be, as we are transferring from the fast on-chip memory to the equally fast L2 memory?)

     Shared (L3) RAM is slower to access by the DSP than from L2.

    • Using my SYS/BIOS 6.3.33 config file, is there a way to turn off L2 caching for this section of memory?   

    Yes, there should be a way. The MAR128[0] DSP register bit needs to be cleared to ensure that the shared (L3) RAM range is not cached into L2. Refer to section 4 of the 674x DSP Megamodule Reference Guide (sprufk5a). I’m not sure how this is done within the SYSBIOS cfg file. I remember how it’s done within the older DSP/BIOS.

    I’ll need to check myself.

    • Would that be a dumb idea (since it would probably turn off L1 caching as well, correct?)

    No. Regardless if L2 is caching from DDR and shared RAM or not, L1 always caches from L2 assuming L1 has been configured as cacheable memory.

    • Optimally, is there a way to turn off L2 caching while keeping L1 caching for this memory?  (I'd be shocked if there was.)

    No, this is not possible. L1 only caches from L2.

    -Mark

  • 0 in reply to Mark Utter
    Intellectual 810 points

    Thanks Mark, that answers that question