Am335x GPMC Multiplexed Address

First, I must say that I am confused with what you are asking.  The title of the post and the last question are consistent, but everything else has me confused.

I believe you are asking for how to connect a 16-bit NOR flash, which has separate address, data and control signals, to the AM335x GPMC when the GPMC is operating in a 16-bt multiplexed mode, correct?

For you other items, I have comments below.

Fred DiNicola said:

Table 7-5 of the TRM shows GPMC_A[17] connected to A16 of a 16-bit device, GPMC_AD[15] is also shown as connected to A16.

Table 7-5 of the TRM shows GPMC_A[17] connect to A16 of a 16-bit device in the "Non-multiplexed Address Data 16-bit device".  This is not consistent with your subject or final question.  If you are intended to connect in multiplexed mode, this column should be disregarded.

Fred DiNicola said:

Table 7-52 shows GPMC_A[16] connected to A16 of a 16-bit device.

Table 7-52 does not even talk about signal connections of the address.  Rather it talks about a NAND interface.  Please clarify what you are referencing.

Fred DiNicola said:

Has anybody implemented a 16-bit NOR FLASH using the multiplexed GPMC_AD[0..15]?

The TRM / Datasheet for the AM3359 has a bit of a conflict. If you want to connect to a Multiplexed Address/Data 16-bit device, you'll need to use the GPMC signals GPMC[11:1].

The IO configuration for these signals say that a mux value of 0 will make them behave as GPMC_A[11:1]. A mux value of 4 will force them to GPMC_A[27:17]. 

To use the GPMC peripheral for a AD Mux device, the IO mux for GPMC_A[11:1] must be set as value 0. 

I have verified these settings on real hardware. 

JayWhy said:

To use the GPMC peripheral for a AD Mux device, the IO mux for GPMC_A[11:1] must be set as value 0. 

I have verified these settings on real hardware. 

I would agree with your findings.  Obviously, you have verified this in hardware and that would be my interpretation of which GPMC address signals are to be used.

JayWhy said:

The TRM / Datasheet for the AM3359 has a bit of a conflict. If you want to connect to a Multiplexed Address/Data 16-bit device, you'll need to use the GPMC signals GPMC[11:1].

The IO configuration for these signals say that a mux value of 0 will make them behave as GPMC_A[11:1]. A mux value of 4 will force them to GPMC_A[27:17].

I'm not sure where the conflict or confusion is located.  The GPMC peripheral has the ability to operate in several modes.  For the multiplexed address/data mode, the functional signals of the GPMC interface, specifically gpmc_a and gpmc_d, have specific meaning.  These signals are then propagated from the GPMC peripheral to the I/Os pins of the device through a bank of IO muxes.  The datasheet Table 2-7 is describing the IO mux value configuration, and has nothing to do with the mode of operation of the GPMC peripheral, which in the scenario happens to be in the multiplexed address/data mode.

The problem is that the signals gpmc_a[11:0] have two possible functions linked to the GPMC peripheral:

mux value 0: gpmc_a[11:0]

mux value 4: gpmc_a[27:a16]

The TRM Table 7-5, center column, says I want to use pins gpmc_a[11:1] as a27:a17 for a 16-bit multiplexed device. Using that table, i set the mux settings to 4. Because the names of the signals at mux value 4 match the names given in Table 7-5. 

HOWEVER, that is not how the system should be configured. THAT is the confusing part. 

The TRM does NOT contain information on the correct IOMUX setting that should be used. 

BrandonAzbell said:

I'm not sure where the conflict or confusion is located

Look at Figure 7-3.  Then look at 7-47.

To me this is contradictory.  On my 16 bit multiplexed NOR flash, where will the GPMC module's GPMC A27-17 show up? Do they map to the "signal names" in the top diagram or the bottom one?  If I know that, then I can correctly map those signals to the proper pins.   It sounds like JayWhy determined the GPMC module's GPMC A27-17 show up as indicated in Figure 7-3 based on his pin settings from the datasheet (i.e.  he's using a mode 0 instead of mode 4 to get the thing to work on "pins" GPMC_A1, A2, etc., which select "signals" gpmc_a1, a2, etc.).  So does this not make Figure 7-47 completely wrong?  Can you confirm that I should be conforming to Table 7-5 and not to Figure 7-47?

Thanks

Great, thanks for the quick turnaround!

Not sure how to "mark this post as answered" but it is answered.

Pat

I

I assume you mean 7-3 is the correct image I do not see a figure 7-5?

I am planning on doing a similar interface using the GPMC and not sure I need all the address bits. I only plan to interface to memory controlled UART devices (XR16L2551) to expand the amount of UARTS. these devices are 8 bit data 3 address lines, CS, R/W signal. I need to know if I can use NON multiplexed mode 8bit data and only the address bits needed (say A0-3 or no address bits only CS) so I can free up the address pins for other functionality like 2 RGMII ports.

If I can use the GPMC without using all address signals my preference would be to have this bus configured as 16bit / 8bit  dependant on CS with a max addressing of 16Mbytes but am trying to get these other options as well. I can get all these without the “local bus” (GPMC) but my colleagues would like to have this bus.

2 RGMII ports

I2C0 and I2C1

MMC1, MMC2

UART1-UART5

USB0, USB1

7 ADC input channels.

And this local bus (GPMC) minimum of adding these expandable UART devices.