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MIPI DSI LCD panel configuration for DSI and DISPC clock setting

abhijit
Intellectual 585 points
Other Parts Discussed in Thread: SYSCONFIG

Hi all ,

          I am working on porting MIPI DSI LCD panel on a custom board with OMAP4460. I am facing problems in clock settings.  The pixel clock according to data sheet is 154MHz. Panel resolution is 1920x1280. SYS_CLOCK is 38.4MHz. Data rate is given 925MHz. RGB888(24 bits per pixel) and i am using 4 data lanes of DSI1 in command mode.  From OMAP4460 Programming manual version F, Figure 10-152 we are following the algorithm. PLL_CLK should be less than 186MHz.  How to get the values for pclk_div, lclk_div, regn, regm, regm_dispc, regm_dsi and lp_clk_div. I have tried with a set of values bu it is failing.

 .clocks = {
                .dispc = {
                        .channel = {
                                .lck_div        = 1,   
                                .pck_div        = 2,   
                                .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                        },
                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
                },

                .dsi = {
                        .regn           = 20,  
                        .regm           = 240, 
                        .regm_dispc     = 3,   
                        .regm_dsi       = 3,   

                        .lp_clk_div     = 10,   /* LP Clock = 8.64 MHz */
                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                },
        },
        .channel = OMAP_DSS_CHANNEL_LCD,
        .skip_init = false,
};

Can you please suggest on this.

Thanks

Abhijit

  • 0
    Intellectual 695 points

    I am assuming you are using DSI Video mode. Unfortunately, I don't think this configuration is possible with OMAP4. As the TRM states, the maximum throughput per data lane is 824Mbps in a 4-data lane configuration. The data rate that you mention seems to be per data lane, and exceeds this limit. You seem to be running 1920x1280@60hz, which is a very demanding configuration. I would suggest to see if you could run your panel in a slower refresh rate (perhaps 30hz).

    Your data rate could have been calculated with the following formula:

    Data rate per lane = PCLK * 24bits / (no. lanes)

    In your case, that is: Data rate per lane = 154 Mhz * 24 / 4 = 924 Mhz.

    The data rate clock per lane (DSI CLK) is simply the data rate per lane divided by 2, since that is a double data-rate clock (DDR).

    So, you basically need to meet two requirements:

    1) The PCLK coming out from Display Controller (DISPC) should be set as follows:

    PCLK = (2 * sysclk * regm) / (regn * regm_dispc * lck_div * pck_div) , if OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC is selected.

    In your case,

    PCLK = (2 * 38.4Mhz * 240 / (20 * 3 * 1 * 2) = 153.6Mhz, which is close enough to your 154Mhz.

    2) The DSI CLK (DDR CLK) should be:

    DSICLK = (2 * sysclk * regm) / (regn * 4), where this 4 in the denominator is fixed. (see CLKIN4DDR clk on TRM).

    In your case,

    DSICLK = (2 * 38.4Mhz * 240) / (20 * 4) = 230.4 Mhz, which is obviously not right since we needed 462 Mhz (924 / 2).

    Even without the hw limitation of 824 Mbps (DSI CLK 412 Mhz) in a 4-data lane configuration, these values for regm and regn wouldn't work.

    lp_clk_div shouldn't matter that much... I have never had any issues with this and this would only matter if you are using Low Power Mode for sending any commands.

    I would suggest, if possible, to try a different configuration for your panel with a lower refresh rate and try to set these values to meet the 2 criteria given here.

  • 0 in reply to Jorge Bustamante
    TI__Prodigy 245 points

    Hi,

    As mention by Jorge, I am suprised it is not a Video mode panel. If it is a command mode then you cannot reach 1920*1280 at 60 FPS

    1/ As line size (1920 pixels) exceed buffer size (960*32-bits), then you will have to use the One-line buffer mode by setting  LINE_BUFFER = 1 in DSI_CTRL

    2/ In Command Mode, there is a limitation limiting Pixel Clock to half of DISPC Functional Clock (LCD=1 and PCD=2), on OMAP4 pixel clock can not exeed  93 MHz.

    So Max FPS you could reach is 37 FPS (93MHz/(1920*1280)).

    you can try to set the below values in appropriate registers and you should obtain a DDR_CLK of 222MHz and reaching approx 30FPS.

     M5_CLOCK_DIV = 4  
     M4_CLOCK_DIV = 4
     PLL_REGM = 185
     PLL_REGN = 15

    Set  LP_CLK_DIVISOR = 15 to obtain a 11.8 MHz LP clock.

    In DISPC, make sure  STALLMODE = 1  in  DISPC_CONTROL and LCD = 1,   PCD = 2 in DISPC_DIVISORn.


      

  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Hi Erwan/jorge,

    Thanks for the reply,

    In the previous post it is mentioned that we are using command mode but we then found that the panel supports video mode.

    We are using video mode and configured for four data lanes.
    The minimum and maximum values given in data sheet are as below,

         ITEM                           SYMBOL         Min.        Typ.             Max.        UNIT
        Vertical Frequency          fV                58             60               62             Hz
        Vertical Period                 tV                 1216        1235           1262          tH
        Vertical Valid                   tVD                               1200                             tH
       Horizontal Frequency      fH                 70             74              78              kHz
       Horizontal Period             tH                 1980         2080           2200         tCLK
        Horizontal Valid              tHD                                1920                            tCLK


    HFP, HBP, HSW, VFP, VBP, VSW values are given as hsw=16, hbp = 32, hfp = 112, vsw = 2, vbp = 16, vfp = 17. These values are defined when horizontal period is 2080 and vertical period is 1235.


    calculated parameters are as below,

        .lck_div     = 1    //Logical clock = 308MHz
        .pck_div     = 2   //Pixel clock = 154MHz
        .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
        .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
     
        .regn         = 20   //Fint = 1.9MHz
        .regm         = 482  //DDR_CLK = 462.5MHz
        .regm_dspc    = 6 //PLL1_CLK1 = 308MHz
        .regm_dsi     = 6 //PLL2_CLK2 = 308MHz
        .lp_clk_div     = 8 //LP_CLK = 38.5MHz
        .offset_ddr_clk = 0,
        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,


        .x_res              =     1920
        .y_res              =     1200
        .pixel_clock     =   154000
        .hfp                  =      112
        .hsw                 =       16
        .hbp                 =       32
        .vfp                   =       17
        .vsw                   =        2
        .vbp                    =       16
        .pixel_size         =     24,


    This gives dsi calculation error as it exceeds the maximum limit.

    We have tried with the horizontal period 1980 and vertical period as 1216 from the minimum values given in datasheet, with active resolution kept at 1920x1200(Pixel clock=137.23MHz).   As it is shown above, minimum and maximum values for horizontal parameters(hfp,hsw,hbp) and vertical parameters(vfp, vsw, vbp) are not mentioned in the datasheet, we tried with hsw = 6, hbp = 12, hfp = 42, vsw = 1, vbp = 7, vfp = 8.

    we are getting the following error
    omapdss DISPC error: GFX_FIFO_UNDERFLOW, disabling GFX
    omapdss DISPC error: SYNC_LOST, disabling LCD
    display0: disable

    Looking forward for your reply

    Thanks

    Abhijit

  • 0 in reply to abhijit
    TI__Prodigy 245 points

    Hi Abhijit,

    I will split the issue into 2 concerns.

    1. Validate DSI and DISPC blanking timings
    2. Validate DISPC settings to resolve GFX underflow. Actually GFX underflow will lead to synclost (data not provided to overlay on time)
    For 1.
    Could you test your settings by disabling all pipelines (GFX and DISPC) and set background color to different values to check correct behavior of panel.
    • set to 0x0 ENABLE bitfield in DISPC_VIDn_ATTRIBUTES and DISPC_GFX_ATTRIBUTES
    • Set background color in DISPC_DEFAULT_COLOR0 registers (RGB888 format) blue =0x000000FF green= 0x0000FF00 red=0x00FF0000

    If 1. passes successfully then for 2.

    Could you

    • Increase GFX fifo low level treshold in DISPC_GFX_BUF_THRESHOLD
    • verify allocation of GFX buffer in DISPC_GLOBAL_BUFFER

    Thanks

    Erwan,

     


     

     

  • 0 in reply to abhijit
    Intellectual 695 points

    Again, I don't think it can work with this configuration...

    1.- You have a DDR_CLK (DSI_CLK) of 462.5 Mhz, which means 925Mbps data rate through one data lane. Unless TRM is wrong, you cannot have more than 824Mbps data rate per data lane in a 4-data lane configuration. In other words, you cannot have a DDR_CLK of more than 412Mhz. Even with minimum values on panel datasheet you would still need a DDR_CLK of ~418Mhz (PCLK*3=1980*1216*58*3), so if datasheet is very strict, your panel might not be able to operate with OMAP4 through this interface. Worth a try is to underclock your panel and try it to make it work with a lower refresh rate; what I would do is to set a OMAP config where you get a DDR_CLK of 412Mhz (or a bit lower?), and keep total blanking time on 1980 for horizontal and 1216 for vertical, this would give you a refresh rate of 57hz, which is quite close to the datasheet minimum.

    2.- Seems like you are selecting PLL1_CLK2 as clock source for DSI_FCLK, and I don't think DSI_FCLK can be this high. Even that I am not sure of the theoretical maximum value for DSI_FCLK, I have practical seen that it must be around ~186Mhz. So, with this configuration you would need to increase regm_dsi to at least to 10 or 11.

    There might be some other restrictions as all the clocks are quite high, but at least I am sure about this two, so I would focus on getting these within the limits to start with.

    The suggestion by Erwan about disabling overlays and check for default color is quite good; this is how I usually test new displays as well.

  • 0 in reply to Jorge Bustamante
    TI__Prodigy 245 points

    Agree with Jorge, DSI and DISPC functional clock are above spec (186MHz and 170MHz max respectively). Also max DDR clock supported by OMAP4 is 450MHz and max LP clock supported by panel are 20MHz, usual freq selected is 10-12MHz.

    Based on your inputs, i have derived a set of timings you could try. I supposed sysclock is 38.4MHz.

    Update your settings with this new one and try  it with disabling overlays and check for default color

    The value below are values that should be in registers. It will give

    • DISPC_FCLK=139.8MHz
    • DSI_FCLK=167.7MHz
    • Pixel clock = 139.8MHz
    • LP clock=11.98MHz
    • 58FPS
    • 4DL video mode
    • RGB888
    • EOT packet enable and sync event mode (no H adn V end packet)
    • No LP transtiion during Horizontal blanking, only during vertical

      DSI_CTRLn
       HSA_BLANKING_MODE = 1
       HBP_BLANKING_MODE = 1
       HFP_BLANKING_MODE = 1
       BLANKING_MODE = 0
       EOT_ENABLE = 1
       VP_HSYNC_END = 0
       VP_HSYNC_START = 1
       VP_VSYNC_END = 0
       VP_VSYNC_START = 1
       LINE_BUFFER = 0
       VP_DATA_BUS_WIDTH = 2

      DSI_CLK_CTRL
       LP_RX_SYNCHRO_ENABLE = 1
       DDR_CLK_ALWAYS_ON = 0
       LP_CLK_ENABLE = 1
       LP_CLK_DIVISOR = 14

      DSI_VM_TIMING1
       HSA = 0
       HFP = 22
       HBP = 20

      DSI_VM_TIMING2
       VSA = 1
       VFP = 10
       VBP = 7

      DSI_VM_TIMING3
       TL = 1485
       VACT = 1200

      DSI_VM_TIMING6

      DSI_CLK_TIMING
       DDR_CLK_PRE = 47
       DDR_CLK_POST = 20

      DSI_VM_TIMING7
       ENTER_HS_MODE_LATENCY = 27
       EXIT_HS_MODE_LATENCY = 24

      DSI_STOPCLK_TIMING (assumes worst case OPP50)
       DSI_STOPCLK_LATENCY = 5

      DSI_VM_TIMING8
       HFPX = 0

    DSI_PHY

      DSI_PHY_REGISTER0     (spec ; min ; max) in ns
       REG_THSPREPARE = 32   (77 ; 50 ; 81)
       REG_THSPRPR_THSZERO = 76   (182 ; 160 ; 189)
       REG_THSTRAIL = 31   (74 ; 78 ; 82)
       REG_THSEXIT = 61   (146 ; 108 ; 150)

      DSI_PHY_REGISTER1
       REG_TLPXBY2 = 12   (29 ; 28 ; 35)
       REG_TCLKTRAIL = 28   (67 ; 71 ; 75)
       REG_TCLKZERO = 112   (268 ; 287 ; 284)

      DSI_PHY_REGISTER2
       REG_TCLKPREPARE = 28   (67 ; 42 ; 72)

    DSIn_PLLCTRL

      DSI_PLL_CONFIGURATION1
       M5_CLOCK_DIV = 9  +1 for encoded value
       M4_CLOCK_DIV = 11  +1 for encoded value
       PLL_REGM = 415
       PLL_REGN = 18

    DISPC

      DISPC_CONTROLn
       STALLMODE = 0
       TFTDATALINES = 3

      DISPC_TIMING_Hn
       HBP = 53  +1 for encoded value
       HFP = 0  +1 for encoded value
       HSW = 4  +1 for encoded value

      DISPC_TIMING_Vn
       VBP = 7
       VFP = 9
       VSW = 1  +1 for encoded value

      DISPC_DIVISORn
       LCD = 1
       PCD = 1

      DISPC_SIZE_LCDn
       LPP = 1199  +1 for encoded value
       DELTA_LPP = 0
       PPL = 1919  +1 for encoded value

  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Hi Erwan,

    Thanks for your response.

    I will be working on these specifications and will let you know shortly.

    Thanks

    Abhijit

  • 0 in reply to abhijit
    Intellectual 585 points

    Hi Erwan,
    We tried with the configuration suggested by you and disabled all the overlays . we COULD Not see any default color on the LCD Panel (but on the HDMI, we could see the default color).

    Our complete structure is as follows . we have some queries on the parameters set ..

    1. With REGM as 415 and REGN as 18 , DDR Clock comes close to 435 Mhz (clkin4ddr = 2* fint * regm) . Would it not exceed the max limit ?
    2. How would we determine Blanking parameters (HFP, HBP, HSW, VFP etc) ? Ideally, we thought these values would be taken from the Panel data sheet only ..
       if we alter these blanking parameters from the panel data sheet, would it still work ?

    Please note that we are now setting dispc_fclk_src as OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC instead of OMAP_DSS_CLK_SRC_FCK .

    static struct omap_dss_device lcd_device = {
        .name            = "lcd",
        .driver_name        = "vvx",  /* panasonic VVX10F 10.1 inch lcd */
        .type            = OMAP_DISPLAY_TYPE_DSI,
        .data            = &dsi1_pana_panel,
        .phy.dsi        = {
            /* Four data lanes and one clock lane used */
            .clk_lane    = 1,
            .clk_pol    = 0,
            .data1_lane    = 2,
            .data1_pol    = 0,
            .data2_lane    = 3,
            .data2_pol    = 0,
            .data3_lane    = 4,
            .data3_pol    = 0,
            .data4_lane    = 5,
            .data4_pol    = 0,

                    .type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
        },
        .clocks = {
            .dispc = {
                .channel = {
                    .lck_div    = 1,    /* Logic Clock = 139.8 MHz */
                    .pck_div    = 1,    /* Pixel Clock = 139.8 MHz */
                    .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
                },
                            .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
            },

            .dsi = {
                .regn = 18,        /*Fint = 2.1*/
                .regm = 415,        /*DDR Clock = 435 MHz Target,*/
                .regm_dispc    = 12,
                .regm_dsi    = 10,
                .offset_ddr_clk = 1,
                .lp_clk_div    = 14,    /* LP Clock = 11.98 MHz */
                .dsi_fclk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
                .tlpx    = 12,
                .tclk = {
                    .zero     = 112, //57,
                    .prepare = 28, //15,
                    .trail     = 28, //15,
                },
                .ths = {
                    .zero     = 76, //22,
                    .prepare = 32, //18,
                    .exit     = 61, //32,
                    .trail     = 31, //18,
                },
            },
        },
    #if 1
        .panel = {
                    .timings = {
                            .x_res          = 1920,
                            .y_res          = 1200,
                            .pixel_clock    = 139800,//65183,
                            .hfp            = 30,
                            .hsw            = 12,
                            .hbp            = 18,
                            .vfp            = 8,
                            .vsw            = 1,
                            .vbp            = 7,
                    },
            },
    #endif
        .ctrl = {
                    .pixel_size = 24,
            },

        .channel = OMAP_DSS_CHANNEL_LCD,
        .skip_init = false,
    }

    Please give me your inputs.

    Thanks
    Abhijit

  • 0 in reply to abhijit
    TI__Prodigy 245 points

    Abhijit

    1. With REGM as 415 and REGN as 18 , DDR Clock comes close to 435 Mhz (clkin4ddr = 2* fint * regm) . Would it not exceed the max limit ?

    If you sys-clock is 38.4MHz, DSI PLL clok is at (2*38.4*415)/(18+1)=1677MHz, this will lead to

    • DDRclock = 1677/4=419.37 MHz ==> 419.37*2=838Mb/s. it is above spec but should work.

    2.  How would we determine Blanking parameters (HFP, HBP, HSW, VFP etc) ? Ideally, we thought these values would be taken from the Panel data sheet only ..
       if we alter these blanking parameters from the panel data sheet, would it still work ?

    No, it will not work. You panel might have some tolerance but  DSI and DISPC need very accurate timings synchronisation to work specially with no line buffer. Be careful your panel data are expressed in pixel where DSI timings are in HSBYTEclock.  There are also other DSI OMAP HW implementation point with some constraint to take in consideration.

    I amnot clue-up on how to fill the DSS structure or other SW parameters but the value i provided should be the values read in the various DSI and DISPC registers.

    For example, you set

                .regm_dispc    = 12,
                .regm_dsi    = 10,

    but in bitfield M4 and M5 in DSI_PLL_CONFIGURATION1 should be set to 11 and 9 respectively (+1 is done in HW)

    I think to validate your setting you will need to dump all DISPC and DSI registers and compare it to my configuration. Value should be identical.

    Keep me posted.

    Thanks

    Erwan



     

  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Hi Erwan,

    We have tried configuring the DISPC and DSI registers exactly according to the timings you derived in your Previous post ..
    And when we dumped the registers from /sys/kernel/debug/omapdss/dsi1_regs, they are having the same values set by us ...
    We could not still see anything on our LCD panel . Following are some of our observations ..

    1. We had tried setting .regm_dispc and .regm_dsi as 11 and 9 respectively .  In Bitfield, M4 and M5 of DSI_PLL_CONFIGURATION1 are set to 10 and 8 respectively .
       With this configuration, we get the following error during bootup

         omapdss DSI error: DSI error, irqstatus 400a0
         DSI IRQ: 0x400a0: RESYNC PLL_LOCK SYNC_LOST     

    2. when we set .regm_dispc =12 and .regm_dsi = 10,  M4 will be set as 11 and M5 will be 9 . With this Setting, We did not get any Error during bootup ...
       But, we get GFX_FIFO underflow error when android starts ...

        omapdss DISPC error: GFX_FIFO_UNDERFLOW, disabling GFX
        omapdss DISPC error: SYNC_LOST, disabling LCD

       We have disabled all pipelines (GFX and Vid1, Vid2 etc) and set some default color ... Even though there are no errors from DSI and DISPC,
       we could not see anything on the panel .

    3. When we dump the clock values, we see the following

        - DSS -
        dpll4_ck 1536000000
        DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666

        - DISPC -
        dispc fclk source = DSS_FCK (DSS_FCLK)
        fck             170666666       

        - DISPC-CORE-CLK -
        lck             170666666       lck div 1

        - LCD1 -
        lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
        lck             139789430       lck div 1
        pck             139789430       pck div 1
        
        - DSI1 PLL -
        dsi pll source = dss_sys_clk
        Fint            2021052         regn 19
        CLKIN4DDR       1677473160      regm 415

        DSS_FCK (DSS_FCLK)      139789430       regm_dispc 12   (off)
        DSI_PLL_HSDIV_DSI (PLL1_CLK2)   167747316       regm_dsi 10     (on)

        - DSI1 -
        dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
        DSI_FCLK        167747316
        DDR_CLK         419368290
        TxByteClkHS     104842072
        LP_CLK          11981951 (With LP_CLK_DIVISOR set to 7)

    4.  We have some confusion on LP_CLK .  We suppose LP_CLK is derived from bitfield LP_CLK_DIVISOR in DSI_CLK_CTRL .
        When we set LP_CLK_DIVISOR to 14 as suggested by you, the LP_CLK what we see when we dump the DSI clocks is HALF of 11.98 MHz, The LP Clock which you          suggested ...  We see that in dsi.c file, lp_clk is calculated as

        lp_clk = dsi_fclk / 2 / lp_clk_div;
     
        I guess, when you suggested 11.98 MHz, we did not consider this (/2 .. (Divided By 2 factor)) ... Correct me if i am wrong ..
      

    5. Now, we think all the values we are setting are proper and in recommendation with the TRM . Also, we satisfy all equations like
       
        VP_CLK x bits_per_pixel = TXBYTECLKHS x NDL x 8 ... etc .. as suggested by the TRM ...

       Is there any other thing which we are missing out here ?

       Thanks

       Abhijit

  • 0 in reply to abhijit
    TI__Prodigy 245 points

    hi Abhijit,

    Log report seems to be aligned with suggested configuration.

    Where you able to probe dsi lanes and measure ddr clock frequency and see the presence of data on DL?

    Could you try to set  DDR_CLK_ALWAYS_ON  to 0x1 maybe your panel requires clock all the time.

    Please provide a dump of DSI and DISPC register.

    Thanks

    Erwan

     

     

  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Now we are trying with the DDR_CLK_ALWAYS_ON set to 0x1. When we probe, we can see the data on all the four data lanes and DDR clock is around 418MHz.

    Following are the  register dump of DSI, DISPC  and CLK with DDR_CLK_ALWAYS_ON set to 0x0.

    REGISTER DUMP OF DSI

                                                          

    DSI_REVISION                        00000030
    DSI_SYSCONFIG                       00000015
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       00000080
    DSI_IRQENABLE                       0015c000
    DSI_CTRL                            00eaca99
    DSI_COMPLEXIO_CFG1                  6a054321
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a0344007
    DSI_TIMING1                         7fff7fff
    DSI_TIMING2                         ffff7fff
    DSI_VM_TIMING1                      00015015
    DSI_VM_TIMING2                      04010807
    DSI_VM_TIMING3                      05cd04b0
    DSI_CLK_TIMING                      00002f1a
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00030000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00487296
    DSI_TX_FIFO_VC_EMPTINESS            1f1f001f
    DSI_VM_TIMING5                      0082df3b
    DSI_VM_TIMING6                      7a6731d1
    DSI_VM_TIMING7                      0012000f
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      20808791
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000004
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20800f80
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20808d81
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20808d81
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     206c1f3d
    DSI_DSIPHY_CFG1                     42061c70
    DSI_DSIPHY_CFG2                     b800001c
    DSI_DSIPHY_CFG5                     ff000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              25633e25
    DSI_PLL_CONFIGURATION2              00656008

    REGISTER DUMP OF DISPC

    DSI_REVISION                        00000030

    DSI_SYSCONFIG                       00000015
    DSI_SYSSTATUS                       00000001
    DSI_IRQSTATUS                       00000080
    DSI_IRQENABLE                       0015c000
    DSI_CTRL                            00eaca99
    DSI_COMPLEXIO_CFG1                  6a054321
    DSI_COMPLEXIO_IRQ_STATUS            00000000
    DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
    DSI_CLK_CTRL                        a0344007
    DSI_TIMING1                         7fff7fff
    DSI_TIMING2                         ffff7fff
    DSI_VM_TIMING1                      00015015
    DSI_VM_TIMING2                      04010807
    DSI_VM_TIMING3                      05cd04b0
    DSI_CLK_TIMING                      00002f1a
    DSI_TX_FIFO_VC_SIZE                 13121110
    DSI_RX_FIFO_VC_SIZE                 13121110
    DSI_COMPLEXIO_CFG2                  00030000
    DSI_RX_FIFO_VC_FULLNESS             00000000
    DSI_VM_TIMING4                      00487296
    DSI_TX_FIFO_VC_EMPTINESS            1f1f001f
    DSI_VM_TIMING5                      0082df3b
    DSI_VM_TIMING6                      7a6731d1
    DSI_VM_TIMING7                      0012000f
    DSI_STOPCLK_TIMING                  00000080
    DSI_VC_CTRL(0)                      20808791
    DSI_VC_TE(0)                        00000000
    DSI_VC_LONG_PACKET_HEADER(0)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
    DSI_VC_SHORT_PACKET_HEADER(0)       00000000
    DSI_VC_IRQSTATUS(0)                 00000004
    DSI_VC_IRQENABLE(0)                 000000db
    DSI_VC_CTRL(1)                      20800f80
    DSI_VC_TE(1)                        00000000
    DSI_VC_LONG_PACKET_HEADER(1)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
    DSI_VC_SHORT_PACKET_HEADER(1)       00000000
    DSI_VC_IRQSTATUS(1)                 00000000
    DSI_VC_IRQENABLE(1)                 000000db
    DSI_VC_CTRL(2)                      20808d81
    DSI_VC_TE(2)                        00000000
    DSI_VC_LONG_PACKET_HEADER(2)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
    DSI_VC_SHORT_PACKET_HEADER(2)       00000000
    DSI_VC_IRQSTATUS(2)                 00000000
    DSI_VC_IRQENABLE(2)                 000000db
    DSI_VC_CTRL(3)                      20808d81
    DSI_VC_TE(3)                        00000000
    DSI_VC_LONG_PACKET_HEADER(3)        00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
    DSI_VC_SHORT_PACKET_HEADER(3)       00000000
    DSI_VC_IRQSTATUS(3)                 00000000
    DSI_VC_IRQENABLE(3)                 000000db
    DSI_DSIPHY_CFG0                     206c1f3d
    DSI_DSIPHY_CFG1                     42061c70
    DSI_DSIPHY_CFG2                     b800001c
    DSI_DSIPHY_CFG5                     ff000000
    DSI_PLL_CONTROL                     00000000
    DSI_PLL_STATUS                      00000383
    DSI_PLL_GO                          00000000
    DSI_PLL_CONFIGURATION1              25633e25
    DSI_PLL_CONFIGURATION2              00656008
    root@android:/sys/kernel/debug/omapdss # cat dispc                            
    DISPC_REVISION                                     00000040
    DISPC_SYSCONFIG                                    00002015
    DISPC_SYSSTATUS                                    00000001
    DISPC_IRQSTATUS                                    00000000
    DISPC_IRQENABLE                                    0116d64e
    DISPC_CONTROL                                      0001832b
    DISPC_CONFIG                                       00020004
    DISPC_CAPABLE                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00ffffff
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00ffffff
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
    DISPC_LINE_STATUS                                  00000390
    DISPC_LINE_NUMBER                                  00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               01101d0b
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00700800
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00004000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               00010001
    DISPC_GLOBAL_ALPHA                                 ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             02cf04ff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               04af077f
    DISPC_CONTROL2                                     00000000
    DISPC_CONFIG2                                      00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX)                        7b9b0000
    DISPC_OVL_BA1(OMAP_DSS_GFX)                        7b9b0000
    DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX)                       04af077f
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 12004098
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             05630640
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   00000000
    DISPC_OVL_BA1(o)                                   00000000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  00000000
    DISPC_OVL_ATTRIBUTES(o)                            00008400
    DISPC_OVL_FIFO_THRESHOLD(o)                        07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000001
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          00000000
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV(o, i)                        00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         00000000
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               00000100
    DISPC_OVL_BA0(o)                                   7b9b0000
    DISPC_OVL_BA1(o)                                   7b9b0000
    DISPC_OVL_POSITION(o)                              00000000
    DISPC_OVL_SIZE(o)                                  02cf04ff
    DISPC_OVL_ATTRIBUTES(o)                            16018018
    DISPC_OVL_FIFO_THRESHOLD(o)                        08630394
    DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
    DISPC_OVL_ROW_INC(o)                               00000a01
    DISPC_OVL_PIXEL_INC(o)                             00000001
    DISPC_OVL_FIR(o)                                   04000400
    DISPC_OVL_PICTURE_SIZE(o)                          02cf04ff
    DISPC_OVL_ACCU0(o)                                 00000000
    DISPC_OVL_ACCU1(o)                                 00000000
    DISPC_OVL_FIR_COEF_H(o, i)                         264c26f4
    DISPC_OVL_FIR_COEF_H(o, i)                         2f481ff2
    DISPC_OVL_FIR_COEF_H(o, i)                         354916f0
    DISPC_OVL_FIR_COEF_H(o, i)                         3b450ff0
    DISPC_OVL_FIR_COEF_H(o, i)                         08404008
    DISPC_OVL_FIR_COEF_H(o, i)                         0f453b01
    DISPC_OVL_FIR_COEF_H(o, i)                         164935fc
    DISPC_OVL_FIR_COEF_H(o, i)                         1f482ff7
    DISPC_OVL_FIR_COEF_HV(o, i)                        243824f4
    DISPC_OVL_FIR_COEF_HV(o, i)                        28391ff8
    DISPC_OVL_FIR_COEF_HV(o, i)                        2d381bfc
    DISPC_OVL_FIR_COEF_HV(o, i)                        32371701
    DISPC_OVL_FIR_COEF_HV(o, i)                        123737f0
    DISPC_OVL_FIR_COEF_HV(o, i)                        173732f0
    DISPC_OVL_FIR_COEF_HV(o, i)                        1b382df0
    DISPC_OVL_FIR_COEF_HV(o, i)                        1f3928f3
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_CONV_COEF(o, i)                          00000000
    DISPC_OVL_FIR_COEF_V(o, i)                         0000f4f4
    DISPC_OVL_FIR_COEF_V(o, i)                         0000f8f2
    DISPC_OVL_FIR_COEF_V(o, i)                         0000fcf0
    DISPC_OVL_FIR_COEF_V(o, i)                         000001f0
    DISPC_OVL_FIR_COEF_V(o, i)                         0000f008
    DISPC_OVL_FIR_COEF_V(o, i)                         0000f001
    DISPC_OVL_FIR_COEF_V(o, i)                         0000f0fc
    DISPC_OVL_FIR_COEF_V(o, i)                         0000f3f7
    DISPC_OVL_BA0_UV(o)                                00000000
    DISPC_OVL_BA1_UV(o)                                00000000
    DISPC_OVL_FIR2(o)                                  04000400
    DISPC_OVL_ACCU2_0(o)                               00000000
    DISPC_OVL_ACCU2_1(o)                               00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
    DISPC_OVL_ATTRIBUTES2(o)                           00000000
    DISPC_OVL_PRELOAD(o)                               000007ff

     

    REGISTER DUMP OF CLK


    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
    - DISPC -
    dispc fclk source = DSS_FCK (DSS_FCLK)
    fck             170666666      
    - DISPC-CORE-CLK -
    lck             170666666       lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck             139789430       lck div 1
    pck             139789430       pck div 1
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck             42666666        lck div 4
    pck             42666666        pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint            2021052         regn 19
    CLKIN4DDR       1677473160      regm 415
    DSS_FCK (DSS_FCLK)      139789430       regm_dispc 12   (off)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2)   167747316       regm_dsi 10     (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK        167747316
    DDR_CLK         419368290
    TxByteClkHS     104842072
    LP_CLK          11981951

    Looking forward for your response.

    Thanks

    Abhijit


  • 0 in reply to abhijit
    TI__Prodigy 245 points

    Hi Abhijit,

    I still see a numbers of discrepencies between the configuration i provided and your regsiters setting:

    DSI configs
      DSI_VM_TIMING1
       HSA = 0  ==> OK
       HFP = 22 ==> actually set to 21 in register
       HBP = 20  ==> actually set to 21 in register
      
     DSI_VM_TIMING2
       VSA = 1 ==> OK
       VFP = 10 ==> actually set to 8 in register
       VBP = 7 ==> OK
      
     DSI_VM_TIMING3
       TL = 1485 ==> OK
       VACT = 1200 ==> OK
     
     DSI_CTRLn ==> OK
     
     DSI_CLK_CTRL
       LP_RX_SYNCHRO_ENABLE = 1 ==> OK
       DDR_CLK_ALWAYS_ON = 0 ==> actually set to 0x0, but need to be 0x1 for LCD bring-up
       LP_CLK_ENABLE = 1 ==> OK
       LP_CLK_DIVISOR = 14 ==> actually set to 7 in register
     
     DSI_PLL_CONFIGURATION1 ==> OK
     
    DISPC configs
      DISPC_TIMING_Hn
       HBP = 53  +1 for encoded value ==> actually set to 17 in register
       HFP = 0  +1 for encoded value ==> actually set to 29 in register
       HSW = 4  +1 for encoded value ==> actually set to 11 in register
      
     DISPC_TIMING_Vn
       VBP = 7
       VFP = 9 ==> actually set to 8 in register
       VSW = 1  +1 for encoded value ==> actually set to 0 in register
     
     DISPC_DIVISORn ==> OK
     DISPC_SIZE_LCDn ==> Ok
     
     
    Please align all above bitfields (commented with "actually set") with given config and make sure other timings DSI_VM_TIMING7, DSI_VM_TIMING8, DSI_PHY_REGISTER0, DSI_PHY_REGISTER1 and DSI_PHY_REGISTER2 are correclty configure.
    The values i provided you are values which should be read in the registers.

    Also you need to configure VC0 SOURCE bit in DSI_VC_CTRL_i[1] to 0x1 to suply DSI with DISPC pixels. In current settings pixels are coming from slave port.

    Thanks
    Erwan,
     

  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Hi Erwan

    Thanks for the reply, We have configured accordingly and register details are as below, nothing is displayed on the lcd panel.

    DSI configs,

    DSI_VM_TIMING1  ----> 00016014
    HSA = 0  
    HFP = 22 
    HBP = 20 

    DSI_VM_TIMING2 ------> 04010a07

       VSA = 1
       VFP = 10
       VBP = 7

    DSI_CLK_CTRL --------> a034600e

    LP_RX_SYNCHRO_ENABLE = 1 
    DDR_CLK_ALWAYS_ON = 1
    LP_CLK_ENABLE = 1
    LP_CLK_DIVISOR = 7


    ***When I see one of the previous posts(july 11), LP clock=11.98MHz is expected and LP_CLK_DIVISOR expected is 14 but with 14 in  LP_CLK_DIVISOR , I can see the  LP clock 5.99 MHz on dumping clk. To achieve 11.98MHz LP clock we gave lp_clk_div as 7 and 0x7 is set in the register. 


    DISPC configs

      DISPC_TIMING_Hn ------>  03500004 
       HBP = 53   
       HFP = 0  
       HSW = 4  

        
        DISPC_TIMING_Vn ------>  00700a01
        
        VBP = 7
        VFP = 9
        VSW = 1

    VC0 SOURCE bit in DSI_VC_CTRL_i[1] is set to 0x1

    Please find the attached log for details on errors and dump of DSI, DISPC and CLK.

    Thanks
    Abhijit

  • 0 in reply to abhijit
    TI__Prodigy 245 points
    Abhijit,
     
    Still some wrong registers settings (NOK):

    DSI_VM_TIMING1  ----> 00016014 ==> OK
    DSI_VM_TIMING2 ------> 04010a07==> OK
    DSI_CLK_CTRL --------> a034600e ==> OK
    DISPC_TIMING_Hn ------>  03500004  ==> OK    
    DISPC_TIMING_Vn ------>  00700a01 ==> NOK
        VBP = 7
        VFP = 9  ==> Set to 0xA in register, should be 0x9
        VSW = 1

    Register dump still shows VC0 SOURCE bit in DSI_VC_CTRL_i[1] set to 0x0.
    Also
      DSI_VM_TIMING7  ==> NOK
            ENTER_HS_MODE_LATENCY = 27   ==> set to 15 in the register
            EXIT_HS_MODE_LATENCY = 24 ==> set to 12 in the register
     
      DSI_PHY_REGISTER0   ==> NOK
          REG_THSPREPARE = 32    ==> Ok
          REG_THSPRPR_THSZERO = 76   ==> set to 108 in the register
          REG_THSTRAIL = 31   ==> OK
          REG_THSEXIT = 61 ==> OK
     
    DSI_PHY_REGISTER1==> OK
    DSI_PHY_REGISTER2==> OK

    DSI_CLK_TIMING ==>NOK
          DDR_CLK_PRE = 47 ==>. set to 43  in the register
          DDR_CLK_POST = 20 ==> set to 22 in the register
     
    Once you have aligned the registers, could you try to disable all vid and gfx pipelines and only use background color, for debugging purpose.
    Could you probe the DSI lanes and check the timings (FPS, vertical porch, TL)
    If it is ok, you can modify the background color to check if data are changing on the lanes.
     
    Otherwise , to remove the GFX underflow you can try to re-allocate unused buffer to the GFX buffer. Refer to DISPC_GLOBAL_BUFFER for re-allocation.
     
    Thanks
    Erwan
  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Hi Erwan,

    Thanks for all your configuration . We are able to get the 1920x1200  LCD panel working with the suggested configuration . There was some issue in our LCD panel because of which it took this much time .. Thanks for your time and co-operation. 

    Regards

    Abhijit

  • 0 in reply to Erwan Petillon
    Intellectual 585 points

    Hi Erwan,

    Thanks for all your configuration . We are able to get the 1920x1200  LCD panel working with the suggested configuration . There was some issue in our LCD panel because of which it took this much time .. Thanks for your time and co-operation. 

    Regards

    Abhijit