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MSGQ blocking my tasks and swis

Pankaj Kumar
Intellectual 300 points

Hello,

We are using TI6670 DSP processor for 4G baseband development. We use MSGQ for  message communication between cores.

We observed using system Analyser that whenever message flows between cores, there starts a HWI (approx 80 microseconds duration) that blocks all our SWIs and Tasks.

We tried using ti.sdo.ipc.transports.TransportShmNotify,  that reduced HWI time significantly, but not still good enough for us.

We would like to have a have a mechanism in which the underneath mechanism for IPC can be de-prioritized in comparision to SWIs.

Is this possible?

Regards,

Pankaj

  • 0
    TI__Mastermind 26780 points

    Pankaj,

    What is your requirement for interrupt latency (i.e., what is “good enough”)? 

    Or are you looking for a non-interrupt based transport mechanism?

    Scott

  • 0 in reply to ScottG
    Intellectual 300 points

    Scott,

    We can handle a Interrupt for about 10 micro seconds (for 5 messages transport). In our case that amounts to 10000 cycles.

    It will be good if we can have a non interrupt based transport mechanism.

    Regards,

    Pankaj

  • 0 in reply to Pankaj Kumar
    TI__Mastermind 26780 points

    Pankaj,

    I asked internally and there isn’t a lower Hwi-latency transport option available.  And there aren’t any planned.  

    For your case it seems messaging performance is less important than Swi preemption cycles, and I don’t think this use case has been requested before. 

    One option would be to write your own transport that implements the ti.sdo.ipc.interfaces.IMessageQTransport interface.  I don’t know if this is feasible for you, but it is one option.

    Scott