Unable read shared memory when Mmu cacheable is true

I running the following code in the omapl137 arm chip.

RTSC.cfg:

var Memory = xdc.useModule('xdc.runtime.Memory');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Startup = xdc.useModule('xdc.runtime.Startup');
var Hwi = xdc.useModule('ti.sysbios.family.arm.da830.Hwi');
var BIOS = xdc.useModule('ti.sysbios.BIOS');

var Cache = xdc.useModule('ti.sysbios.family.arm.arm9.Cache');

var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');

// Enable the cache
Cache.enableCache = true;
// Enable the MMU (Required for L1 data caching)
Mmu.enableMMU = true;

descriptor attribute structure
var SharedAttrs = {
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
bufferable: true, // bufferable
cacheable: true, // cacheable
};
var SharedBaseAddr = 0x80000000; // substitute the 1MB base address of your peripheral here
Mmu.setFirstLevelDescMeta(SharedBaseAddr, SharedBaseAddr, SharedAttrs);

Dsp exchange() with Arm by hardware interrupt SYSCFG_CHIPINT0. 

ARM-DSP communication, is as follows:
1. ARM writes a command in the shared memory.
2. ARM interrupts DSP.
3. DSP responds to the interrupt and reads the command from the shared memory.
4. DSP executes a task based on the command.
5. DSP interrupts ARM upon completion of the task.

It causes no problems at the DSP side (thre is no OS over there). But at the ARM side (it uses sysbios) there is no any data received from the DSP in the shared memory but at the same time there is a data received in the memory browser.

What is wrong in this code?

#pragma DATA_SECTION(".BuffMemD2A")
unsigned int BuffMemD2A[0x200];

#pragma DATA_SECTION(".BuffMemA2D")
unsigned int BuffMemA2D[0x200];

HOSTDATAD2A HostdataD2A; // no matter struct
HOSTDATAA2D HostdataA2D; // no matter struct

Void TaskChip0(UArg a0, UArg a1)
{
WaitChip();

while(TRUE)
{
if( ChipTxRxGet() )
{
int * pDataD2A = (int *)&HostdataD2A;
int * pDataA2D = (int *)&HostdataA2D;
int * pBuffD2A = (int *)BuffMemD2A;
int * pBuffA2D = (int *)BuffMemA2D;

volatile unsigned int lA2D;
volatile unsigned int lD2A;

for(int i = 0; i < 25; i++)
{
lA2D = pDataA2D[i];
lD2A = pBuffD2A[i];
pBuffA2D[i] = lA2D;
pDataD2A[i] = lD2A;
}
ChipTxRxClr();
}
Task_sleep(1);
}
}
//------------------------------------------------------------------------------------
Void IsrChip0(UArg arg)
{
ChipTxRxSet();
ChipInt0Clr();
Hwi_clearInterrupt(28);
}
//------------------------------------------------------------------------------------
Void IsrChip1(UArg arg)
{
ChipSyncSet();
ChipInt1Clr();
Hwi_clearInterrupt(29);
}
//------------------------------------------------------------------------------------
int main()
{
ChipIntSetup(); // setup sync bool type flag

Hwi_Params HwiParams;
Hwi_Handle hHwi;
Task_Handle hTask;
Task_Params TaskParams;

Hwi_Params_init(&HwiParams);
Task_Params_init(&TaskParams);

HwiParams.arg = 28;
HwiParams.enableInt = FALSE;
hHwi = Hwi_create(28, IsrChip0, &HwiParams, NULL);
if (hHwi == NULL)
{
System_abort("Hwi create failed");
}

HwiParams.arg = 29;
HwiParams.enableInt = FALSE;
hHwi = Hwi_create(29, IsrChip1, &HwiParams, NULL);
if (hHwi == NULL)
{
System_abort("Hwi create failed");
}

TaskParams.stackSize = 1024;
TaskParams.priority = 15;
hTask = Task_create((Task_FuncPtr)TaskChip0, &TaskParams, NULL);
if (hTask == NULL)
{
System_abort("Task create failed");
}

Hwi_enableInterrupt(28);
Hwi_enableInterrupt(29);

BIOS_start(); // enable interrupts and start SYS/BIOS
}