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Ensuring C6678 DSP Clocks are High-Z During Power Up

Richard Marsh
Intellectual 760 points
Other Parts Discussed in Thread: CDCE62005


The C6678 data manual states:

"The clock input buffers for CORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK and MCMCLK
use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until
CVDD is at a valid voltage level."

The C6678 EVM uses two CDCE62005 for these clocks. How does it meet the above requirement for these clock pins to be tri-state before CVDD is applied?

Does it use the power down feature of the CDCE62005? The datasheet is ambiguous about the state of the output pins in powerdown:

- The "Electrical Characteristics Operating Conditions" for LVDS outputs (pg 16) shows for the powerdown output current that Vo is VCC or 0V i.e. not tri-state
- Fig 23. "Device State Control Diagram" says the output buffer is Hi-Z in the powerdown state. Incidentally the power-on-reset state has the output drivers set to "OFF". How is that different from Hi-Z?

Thanks,

Richard

  • 0
    TI__Mastermind 42545 points

    The Power_down control signal is sequenced by the FPGA to ensure that the outputs of the CDCE62005 are not actively driven before the CVDD voltage is present.  Although the data sheet is vague on this point we checked with the clocking team that supports that part to be sure that is was in an acceptable state for the C6678 as long as the Power_down control signals was asserted.