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Why QMSS/CPPI is required in DirectIO SRIO

Hi All,

          I have little background on SRIO from 6488 DSP device. Following are my doubts in SRIO difference w.r.t to c6670

1. DirectSRIO works by doing write/read on Memory of other device [Memory map of READER CHIP CORE would be known at WRITER CHIP CORE]? So DirectIO is independant of QMSS/CPPI? Kindly help me in understanding where does this QMSS/CPPI fit in between ?

2. If i take SRIOLoopBackDirectIOISRexample project and SRIO_TputBenchmarkingproject, in both projects there are cases of DirectIO and in both cases QMSS/CPPI is used. I am not able to follow what role does the QMSS/CPPI play?

3. Can someone please explain the following line w.r.t to qmss/cppi [SRIO_LLD_SDS.pdf]

"To ensure that the driver executes across multiple cores and to satisfy the requirements of multiple applications which use the driver; the driver exposes a concept called “Driver Instances”.Each driver instance needs to configure various CPPI & QMSS parameters before it can be used.

Please explain in simple terms [point by point], i am really confused on this.

Thanks

RC Reddy