I was looking through the design-in guide for the TPS65023 (http://processors.wiki.ti.com/index.php/OMAP35x-AM37x-DM37x_with_TPS65023:_Design_In_Guide) and was a little confused about two diagrams which which show the 32k oscillator circuit AND'ed with the 1.8V power good signal.
Under the heading "Power Down Sequencing", the text notes:
During power down, all signals driving OMAP35x or AM/DM37x should have a voltage level equal or less than the I/O voltage of OMAP35x or AM/DM37x to avoid driving pins that are unpowered.
Looking at the diagram in this section, it appears the solution is using the AND gate to mitigate this issue by keeping the output at logic level low when 1.8VPG signal is low. However, if the AND gate and the processor's IO rail use the 1.8V source, wouldn't this be a non-issue? Perhaps the signal is AND'ed for a different reason?
A similar diagram is present under the heading "32KHz clock circuit". I completely understand the need for something to sharpen the edges of the clock signal, but it is not clear why the clock must be gated with 1.8V power good signal.
Thanks - AM