C66 Power sequence

1)  The only clocks that are required to be valid during the reset process are the CORECLK and the DDRCLK.  These clocks are used by the core while the part is held in reset and must be present for the reset to complete correctly.  The rest of the clocks must be present before the IP they support are released from reset.  Depending on the boot mode you've selected an IP may be used by the ROM bootcode so the best practice is to start driving all the clocks that you are using in your design after CVDD is present.

2)  AVS is an acronym for Adaptive Voltage Scaling.  An app note describing AVS can be found at the following link. http://www.ti.com/lit/ml/slyb186/slyb186.pdf

3)  CVDD is the AVS core voltage and CVDD1 is the fixed core voltage.

4)  The LJCB clock buffers are differential input buffers and holding one leg high and one leg low will ensure that the clock will remains static internal to the part.

5)  There is an issue with RESETSTAT that is described in Advisory 19 of the errata document.  While it was intended that RESETSTAT would be driven low when either the CVDD or the DVDD18 voltages were present it is actually only valid when DVDD18 and CVDD are present.  Please see the workaround in the advisory.

6)  There is no clear indication of a transition between these two phases because they may overlap.  The line drawn in the power sequencing document is an attempt to illustrate that the power must be stable before the device can finish the initialization process.  There are two basic requirements that must be met before PORz can be released.  The first is that all the power supplies must be active and stable for 100usec. This is represented by time 5 in the sequencing tables.  Once this parameter is met the power stabilization phase has completed.  The second is that SYSCLK1 must toggle at least 500 times before PORz can be released.  This requires a delay of at most 16usec from when the clock begins to toggle to the release of PORz.  This delay may be concurrent with the 100usec delay associated with the power sequencing or it may follow the 100usec.  If it's concurrent the device initialization phase will begin before the power stabilization phase is complete.  Regardless, as long as the sequencing requirements are met the device will initialize correctly.

7)  Originally the maximum clock period was was 33.3nsec (30MHz) and was reduced to 25nsec (40MHz) during the characterization of the part.  This reduces the minimum time from when the clock starts toggling to the release of PORz to 12.5usec but 16usecs was still a valid delay so we didn't change the diagram. 

8)  A number of internal parameters used during initialization are stored fuses that are programmed during the device factory testing, for example the smart reflex voltage level for the part.  These are scanned during initialization to configure the part.

6.  That is correct.  Device initialization will continue until the RESETSTATz signal is driven high.

7. I'm sorry for the confusion. The sequencing requires the SYSCLK1 to be present for 500 cycles.  SYSCLK1 is the output of the main PLL which is bypass during the initialization so it is essentially equivalent to the CORECLKP/N input.  The cycle time range for CORECLKP/N is specified as 3.2ns to 25ns which is equivalent to a frequency range of 312.5MHz to 40MHz.  Originally the spec was from 312.5MHz to 30MHz or 3.2ns to 33.3ns but it was determined that 30MHz was too slow for proper operation.  That is where the 33.3ns number came from originally.

We need 500 clock cycles to initialize the part but most customers would rather have a required delay from when the clock is present to when the PORz can be released.  Of Course this delay will vary depending on the clock cycle time of CORECLKP/N.  To ensure that we had a delay that would be valid for all clocks we took the longest cycle time and multiplied it by 500 to get the delay in the sequencing section.  At some point that number was rounded to 16us.  Since the longest cycle time had been reduced to 25ns the 16us was still long enough to provide a delay for any clock used so we didn't change that number.