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SRIO port_ok toggling

tscheck
Mastermind 23525 points

We have seen occasions where a marginal link seems to show higher than normal CRC errors and even a fatal error that requires software to recover.  The situations that we have observed happens after a reset to one of the link partners.  Even with the error recovery steps and ACKID alignment steps that are outlined in other threads, the issue may show up as a very long delay to recover the link before being able to send packets.  What we've determined through some testing is that the port_ok bit actually toggles on some of these links, and depending on when and how often it toggles, this can cause havoc on the physical layer statemachines and cause some of these error states.

  • 0
    TI__Mastermind 23525 points

    Change the VMIN_EXP field in the RIO_PLM_SPn_VMIN_EXP register(s)  to 15.  We've had very good results in doing so.  Effectively, it increases the number of error free 8b/10b comma code groups needed before declaring lane synchronization, thus avoiding or at least limiting the possibility of port_ok toggling.  Note that the default value for this register is 0, and is not modified by the DSP boot ROM.  If you are booting via SRIO, you will need to change this value on the attached link partner, which has the same effect.

    Regards,

    Travis

  • 0 in reply to tscheck
    Mastermind 6325 points

    Hello Travis,

    Is this the code you are expecting? Do you mean 15 decimal or 0x15?


    SRIO_PLM_VMIN_EXPONENT vminExponentConfig;
    /* Configure the PLM for all the ports. */


    for (i = 0; i < 4; i++)

    {

    /* Set the PLM Port Silence Timer. */

    CSL_SRIO_SetPLMPortSilenceTimer(hSrio, i, 0x2);

    /* TODO: We need to ensure that the Port 0 is configured to support both

    * the 2x and 4x modes. The Port Width field is read only. So here we simply

    * ensure that the Input and Output ports are enabled. */

    CSL_SRIO_EnableInputPort(hSrio, i);

    CSL_SRIO_EnableOutputPort(hSrio, i);

    /* Set the PLM Port Discovery Timer. */

    CSL_SRIO_SetPLMPortDiscoveryTimer(hSrio, i, 0x2);

    /* Reset the Port Write Reception capture. */

    CSL_SRIO_SetPortWriteReceptionCapture(hSrio, i, 0x0);

    /*Set VMIN to 15 as recommended by this post:

    * http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/196080.aspx */

    CSL_SRIO_GetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);

    vminExponentConfig.vminExp = 15;

    CSL_SRIO_SetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);

    }

  • 0 in reply to Brandy Jabkiewicz
    TI__Mastermind 23525 points

    Yes, sorry Brandy, it is 15 decimal, a 4b field.  Set it to 0xF.

    Regards,

    Travis