one 16 bit ddr3 memories for each bank

Hi Iai,

Please see chapter DDR2/3/LPDDR1 Memory Controller in our Technical Reference Manual (TRM) on our product page.

BR,

Viet

hi Viet,

I am using two 16-bit DDR3 (1Gb), and connecting one to each bank by lower 16bit data bus. In CCS, the data read from memory (0x80000000 and after) only shows the lower 16bit, and higher 16bit is always zero.

The GEL for DMM setting is :

==========

#define    DMM_BASE_ADDR   0x4E000000

//-DMM & EMIF4 MMR Declaration

#define DMM_LISA_MAP__0     (DMM_BASE_ADDR + 0x40)

#define DMM_LISA_MAP__1     (DMM_BASE_ADDR + 0x44)

#define DMM_LISA_MAP__2     (DMM_BASE_ADDR + 0x48)

#define DMM_LISA_MAP__3     (DMM_BASE_ADDR + 0x4C)

#define DMM_PAT_BASE_ADDR     (DMM_BASE_ADDR + 0x460)

WR_MEM_32(DMM_LISA_MAP__0, 0x80440300);  

WR_MEM_32(DMM_LISA_MAP__1, 0xC0440310);  

WR_MEM_32(DMM_LISA_MAP__2, 0x80440300);  

WR_MEM_32(DMM_LISA_MAP__3, 0xC0440310);

WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);

==========

I have read about DMM in SPRUGZ8a.pdf, but still qute confuse what to do.

Please help to advise.

Thanks,

hal