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How to configure GPMC to make it access CPLD with synchronous single mode?

Zhifeng Zhang1
Prodigy 60 points

Hi,

I want to using GPMC to access a CPLD in my target, I configured GPMC with following parameters, but GPMC clock only occurs once when I access CPLD at the first time. After that there is no clock is sent, why?

The following is detailed GPMC configuration:

1. firstly I configure CS3 as mode 0 since I use it as chip-select

2. configure CONTROL.CONTROL_PADCONF_GPMC_NCS7[24] INPUTENABLE1 = 1, using is as gpmc clock.

3. configure GPMC registers:

AM3X_GPMC_CONFIG1_3 = 0x28001000: configure read/write as synchronous mode, 16bit device, NOR like

AM3X_GPMC_CONFIG2_3 ~ AM3X_GPMC_CONFIG6_3: default value

AM3X_GPMC_CONFIG7_3 = 0x00000f58: I configured base address as 0x18000000 with 16M size

 Is there other anything need to do? Why only the first time can send clock, but after that there is no clock any more?

Does I need to enable gpmc clock? where can I configure it?

  • 0
    Prodigy 60 points

    Hello,

    I have made progress in this question:

    1. for write, it can work OK.

    2. For read, the clock only send once during the first time I read CPLD, and,  I only read 1 word, but the clock is more than 200(why so many?).

    I am going to remove the CPLD to test timing!

  • 0 in reply to Zhifeng Zhang1
    Prodigy 60 points

    The question is solved.

    It is not question of CPU, it is not a question of CPLD device, it is not a question of timing!

    It is because of CACHE access!!

    In Nucleus OS, firstly the CPLD mempry area must be registered(or be known by OS). I registered it as a cache device. So when I read it firstly, next when I read it, OS obtain value from cache directly instead of sending clock to read physics memory!

    Now I knew ti shoule be a NOCACHE device as CPU peripheral.