Hello,
we're having a problem configuring the GPMC for a 16 bit SRAM in muxed mode.
The timing setup seems to be ok (oscilloscope checked).
But when writing six 8bit values successively at addresses 0,1,2,3,4,5 and then reading these six addresses back, the values are mixed:
WRITE:
g_pu8SRAM[0] = 0x11;
g_pu8SRAM[1] = 0x22;
g_pu8SRAM[2] = 0x33;
g_pu8SRAM[3] = 0x44;
g_pu8SRAM[4] = 0x55;
g_pu8SRAM[5] = 0x66;
READING BACK (addresses 0,1,2,3,4,5)
0x55
0x22
0x11
0x44
0x33
0x66
But: when writing and reading alternating (write address 0, read address 0 etc.), all the values read back are correct.
When looking at the SRAM memory with Visual Studio remote debugger, we encountered another issue. It seems that with every byte write, it is written to the correct address but also to address 0 !?
We are a little puzzled right now, so hopefully, you can provide help on where to look at next.
Thanks in advance.
Best regards, Timm.
Here are the GPMC register settings:
pGPMC->GPMC_CONFIG1_1 = (
( ((DWORD)1) << 9 ) | // address and data multiplexed attached device
( ((DWORD)1) << 12 ) // devicesize 16bit
);
// Chip select timing CS1
pGPMC->GPMC_CONFIG2_1 = (
( ((DWORD) 4) << 0 ) | // chip select ON time [0..15 clk] from start of cycle
( ((DWORD)15) << 8 ) | // chip select RD OFF time [0..31 clk] from start of cycle / M5M5W816TP-55HI: min 55ns -> @133Mhz -> 8*7,5ns=60ns
( ((DWORD)15) << 16 ) // chip select WR OFF time [0..31 clk] from start of cycle / M5M5W816TP-55HI: min 55ns -> @133Mhz -> 8*7,5ns=60ns
);
// ADV / ALE timing CS1
pGPMC->GPMC_CONFIG3_1 = (
( ((DWORD) 2) << 0 ) | // AdV ON time [clk 0..15] from start of cycle -> 1 (address is at input of d-latch at start of cycle, latch it after 1 cycle)
( ((DWORD)15) << 8 ) | // AdV RD OFF time [clk] from start of cycle -> must be OFF whole Rd cycle (addr. needs to be stable whole cycle)
( ((DWORD)15) << 16 ) // AdV WR OFF time [clk] from start of cycle -> must be OFF whole Wr cycle (addr. needs to be stable whole cycle)
);
// nWE / nOE timing CS1
pGPMC->GPMC_CONFIG4_1 = (
( ((DWORD) 4) << 0 ) | // nOE ON time [clk 0..15] from start of cycle -> drives the address bus until nOE assertion time (ie until nOE on time)
( ((DWORD)15) << 8 ) | // nOE OFF time [clk 0..31] from start of cycle
( ((DWORD) 4) << 16 ) | // nWE ON time [clk 0..15] from start of cycle
( ((DWORD)13) << 24 ) // nWE OFF time [clk 0..31] from start of cycle
);
// RdAccessTime and CycleTime timing CS1
pGPMC->GPMC_CONFIG5_1 = (
( ((DWORD)15) << 0 ) | // Rd cycle time [clk 0..31] from start of cycle
( ((DWORD)15) << 8 ) | // Wr cycle time [clk 0..31] from start of cycle
( ((DWORD)10) << 16 ) | // Rd access time [clk 0..31] from start of cycle
( ((DWORD) 1) << 24 ) // PAGEBURSTACCESSTIME [clk 0..31] from start of cycle
);
// WrAccessTime, WrDataOnADmuxBus timing CS1
pGPMC->GPMC_CONFIG6_1 = (
( ((DWORD)1) << 0 ) | // Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write)
( ((DWORD)1) << 6 ) | // Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type)
( ((DWORD)1) << 7 ) | // Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type)
( ((DWORD)10) << 8 ) | // CYCLE2CYCLEDELAY Chip-select high pulse delay between successive accesses (0..15 clk)
( ((DWORD)6) << 16 ) | // WRDATAONADMUXBUS (1 clk after ADV off, at which address is latched)
( ((DWORD)1) << 24 ) // Write access time [clk 0..31] from start of cycle -> used as wait time in async mode
);
// address mapping configuration CS1
pGPMC->GPMC_CONFIG7_1 = (
( ((DWORD) 1) << 0 ) | // CS1 base address 0x1000000
( ((DWORD)15) << 8 ) // CS1 mask address. 0x1111: Chip-select size of 16 Mbytes
);
// Enable CS1
pGPMC->GPMC_CONFIG7_1 |= (
( ((DWORD) 1) << 6 ) // CS1 enable
);
