This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interfacing to EMIF16 of C6678

Other Parts Discussed in Thread: SN74LVCH16T245

Hi Sir,

We have a design using  X16 Nor Flash for boot purpose of C6678. 

In page 15 of EMIF16 userguide sprugz3a.pdf , it is said that  "EMIFA[23:22] behave as address selects. For 16-bit interface, EMIFA23 is connected to address pin A0 of the ASRAM/NOR Flash." , But the Nor Flash we used do not have address pin A0, the least  significant address bit is A1 instead.

Should we connect A23 to A1 (which means  EMIFA [22:0, 23] to our A[N:0] ) in our design?  Thank you very much.

  • Some manufacturers have different ways of documenting the address bus on NOR devices, especially the ones that can support either an 8bit or a 16bit data bus.  Can you give me the manufacturer and part number for the NOR flash?

  • Hi Bill,

    The NOR Flash we are using is PC28F128P30B85 from Micron.

    Thank you very much.

  • Hi Bill,

    The NOR Flash we are using is PC28F128P30B85 from Micron.

    Thank you very much.

  • I've looked over the datasheet.  For this device the address mapping would be as follows.

    EMIFA23 -> Flash A1

    EMIFA00 -> Flash A2

    EMIFA01 -> Flash A3

    ...

    EMIFA21 -> FLASH A23

    The chip select used should be configured for a 16bit width.

  • Thank you very much, Bill.

  • Dear Bill,

    we are interfacing EMIF16 6678 with IDT7024 4K*16 DPRAM (ASRAM). Can i connect A0 to A11  6678 to A0to A11 of DPRAM for 16BIT interface.

    As per 6678 recommendation for 16 BIT interface i need to connect A23 of DSP6678 to A0 of DPRAM , A1 to A11 of 6678 to A1 to A11 of DPRAM.

    should we connect  or we need to change ?.

    Also we are using level shifter sn74lvch16t245 in between DSP & DPRAM  for 1.8V to 5V level translation.

    Also we are enabling OE# SN74LV levelshifter for 16 bit data bus with CS0 and CS1 chip selects of DSP6678 with 1.8v AND gate(tpd-2ns).

    Propagation delay for latch & and gate is arround 30ns(worst case). Can i interface 6678 with 25ns DPRAM ?

    or i need to connect to 35 or 55ns DPRAM ?.

    Thanks & regards,

    Prasad.

  • Hi Prasad,

    The connection should be close to the one shown in Figure 2-2 of the Keystone EMIF users guide.  The addressing will be as follows for the IDT 7024.

    Keystone                    IDT7024

    EMIFA23      ->          A0

    EMIFA00      ->          A1

    EMIFA01      ->          A2

        ……………………

    EMIFA09      ->       A10

    EMIFA10      ->       A11

     

    You will need two of the level translators, one for the data and one for the address and command signals.  Using the CE to control the OE on the buffer should work but you’ll have to do a timing analysis to determine what the wait times needed.  The buffer has pretty wide windows so that will require that you add to the length of your bus cycles to ensure the data is present for the time needed.  Don’t forget that this is a dual port memory so you might have to connect the busy signals to the EMIFWAIT to extend a cycle if the memory is being accessed from the other side.

    Regards,   Bill