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Change descriptor pool memory from L2 to DDR3 in Qmss demo ?

my shin
Prodigy 30 points

HI.

I am running PDK demo in CCS 5.1.1.

- Project : qmInfraExampleProject
- CCS 5.1.1

- pdk_C6670_1_0_0_20
- 6670 EVM
TI original demo source runs in 6670 EVM. --> OK

But, I want to change descriptor pool memory from L2 to DDR3 or MSMC.

= modification =
1 Add DDR3 segment
SECTIONS
{
.init_array: load >> L2SRAM
.qmss: load >> L2SRAM
.cppi: load >> L2SRAM

.ddr3_data : load >> DDR3
cppiLocalHeap: load >> L2SRAM
}

2. not convert global address for DDR3
static UInt32 l2_global_address (UInt32 addr)
{
UInt32 corenum;

if (addr & 0xFF000000)
{
/* Address is already global, return */
return (addr);
}

/* Get the core number. */
corenum = CSL_chipReadReg (CSL_CHIP_DNUM);

/* Compute the global address. */
return (addr + (0x10000000 + (corenum * 0x1000000)));
}

3. place the descriptor pool memory at DDR3
- #pragma DATA_SECTION (hostDesc, ".ddr3_data");
- #pragma DATA_SECTION (monolithicDesc, ".ddr3_data");


4. result
[TMS320C66x_0] --------------------Transmitting packets----------------------
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@80000000
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@80000040
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@80000080
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@800000c0
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@80000100
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@80000140
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@80000180
[TMS320C66x_0] Core 0 : Transmitting descriptor 0x@800001c0
[TMS320C66x_0]
[TMS320C66x_0] -------------------------Queue status-------------------------
[TMS320C66x_0] Transmit Queue 800 Entry Count : 0
[TMS320C66x_0] Tx Free Queue 736 Entry Count : 0
[TMS320C66x_0] Rx Free Queue 737 Entry Count : 16
[TMS320C66x_0] Receive Queue 704 Entry Count : 8
[TMS320C66x_0] Tx completion Queue 1000 Entry Count : 0
[TMS320C66x_0]
[TMS320C66x_0] --------------------Receiving packets-------------------------
[TMS320C66x_0] Core 0 : Received descriptor 0x@80000200 of length : 0
[TMS320C66x_0] Error Core 0 : In data buffer Tx: X - Rx: X
[TMS320C66x_0] Error Core 0 : In data buffer Tx: X - Rx: X
[TMS320C66x_0] Error Core 0 : In data buffer Tx: X - Rx: X

What's WRONG ?




  • 0
    TI__Genius 12805 points

    The first response that I have is to look at the cache.  By moving from L2 to DDR (say) and enabling the cache, you must keep cache coherency between masters.  Try to disable the cache and repeat the experiment. If the problem persists, post again

  • 0 in reply to ran35366
    Prodigy 30 points

    Disable the cache. such as 

    main()

    {

    Cache_disable( Cache_Type_ALL );  /* cache function at first line of main() */

    ....

    }

    But, the result is same. Simulator mode shows same result.

    Attached the source code.

    What's problems ??..



  • 0 in reply to my shin
    TI__Genius 12805 points

    I was able to reproduce your results on my 6678 board.   It requires more investigation.  Stay tuned

     

    Thanks    Ran

  • 0 in reply to ran35366
    TI__Genius 12805 points

    One more thing

     

    I notice that when I run it, I get error in memory region insert.  Make sure that the address of teh memory region is in order.  (Read the document if needed)

    That is, the global address of the first memory region that is inserted, MUST be lower than the global address of the second memory region

     

    And the second must be lower than the third and so on.

     

    Make sure this is the case in your code

    Ran

  • 0 in reply to ran35366
    Prodigy 30 points

    I know that the memory region must be in order.

    In my code, the memory region insert is no errors in run time.

    - myshin -