My case is that DM8168 is PCIe RC,and FPGA is PCIe EC.
http://processors.wiki.ti.com/index.php/TI81XX_PCI_Express_Root_Complex_Driver_User_Guide
"Reset/Power on sequence
Explore changing power up sequence across RC & EP(s). For example:
Power up EP before RC.
Note that is may not be straightforward in case when using refclk sourced from RC board. That is, you will still need to ensure that the refclk is provided to the note which is powered up first
Also, it is possible that the h/w is configured such that a reset is applied to downstream when RC is powered up. In such case, try to isolate the downstream from this reset.
Depending upon the observations in the above step, you may need to time the reset sequence for final system."
according to the above note.I should power the fpga first,and power up the DM8168?
and the last two points is not so clearly for me.
I should isolate or control the PCIe reset line manually?
and you may need to time the reset sequence for final system.What 's the meaning?I should calculate the reset time sequence carefully?
thank you in advance.