Please find attached snap-shots. It contains the reset interface with the processor DM8107.
In the datasheet it is mentioned that when internal watchdog timer of processor overflows, a low pulse is generated on the output of the pin AJ30 (shown in watchdog_circuit_2).
In rest of the cases, it should be high.
Case1: When the circuit is same as shown in the figure, then processor remains in the reset state only and at that time at regular interval pulses are generated on the AJ30 pin.
As per datasheet, this should not happen.
Case2: To bring the processor out of reset, I have opened the R28 resistor and processor came out of reset. But now, when the internal timer overflows, processor stops sending Watchdog pulses.
Please go through it and please let me know if you want any additional detail.
Thank you,
Regards,
Vishal Dhanani.