How to use C6457 EMIFA in synchronous mode?

Another question, do I have to set EDMA to read/write data from FPGA?

sorry!! I'm a freshman about using DSP, so there is a lot of question.

Could anyone explain more carefully?

Thanks a lot!!!

Hello,

The synchronous transfer mode for EMIF deals only with the way data is exchanged. The exchange itself (burst) may be any length between 1 and n words, depending on DSP internal scheduling : for example an EMIF request to another domain or an interrupt (if soft-managed transfer) may suspend the current burst. In your case, bursts of four 16-bit words (64-bit) are generated, probably due to the memcpy function doing 64-bit read-writes.

SOE can't (must not) be manually controlled; however, if no use of other EMIF domains nor EDMA, you may program the whole block read through an EDMA transfer. If no wait state, no arbitration conflict,... the burst will be full size.

If possible, a far safer option is to make the FPGA able to cope with non-continuous transfers (simple cycle-by-cycle read request through the read command signal CEn, each with your 2-cycle read latency). This would enable both accesses (software and EDMA) in all scheduling cases.

Jakez

Dear Jakez,

First, thank you for your reply.

I still have several problems

1. According to the code which I posted above, is there anything else I have to set to before use EMIFA? Did I miss anything??

2. I use logic analyzer to check the waveform. When DSP read data through EMIF, the waveform of SOE just shows as describe before, but DSP can get the data from FPGA.

When DSP write data to FPGA, the waveform of SWE can keep active low for a quit long time and the data change with EMIFA_clk (just like sync mode), but the value which FPGA received is not right. It's strange.

thanks!!!

Eric

Hello,

Sorry, I don't use CSLs, so I can't confirm you the way you use these functions.

There is only a few parameters to configure EMIF in synchronous mode, the most critical are the read and write latencies which depend on the FPGA interface. For example using a 2-cycle read latency while the FPGA expects a unique cycle may also explain sample swallows, as the DSP will ignore first sample in each burst (and symetrically for write latency).

Jakez

Dear Jakez,

First still thank you for your reply.

I know that there are only few parameters have to set in synchronous mode, and I think I'm already do that.

But the result still not right. For example, I change the latency to 3 or 1 cycles, but in LA, the waveform of SOE still have 2 cycles latency.

I don't know what I miss??

I read the data manual of C6457 (SPRS582B).

Is the EMIFA setting related to Megamodule setting??

In SPRS582B P80~81, seems that I have to set some registers before I use these region (CE2~CE5).

Is that right?? and how do I set these registers??

These problems bothered me for a long time, so is there any TI' employees can help me to solve these?

Even you can give me a detail sample code about how to use EMIFA to transmit data. (include what I have to set in CCS5 environment)

Thank you very very very much!!!

Eric

Hello again,

In the sprs582 pp80-81, the MARn registers need to be set to 0 for the FPGA region(s) at system init (before cache init/reset), disabling cache in non-memory CEn domains (MARn are 0 at reset, see cache in megamodule user's guide spru871k.pdf). The megamodule and the EMIFA are independant subsystems.

Can you give the CEnCFG register value with your different settings, to check with EMIF user's guide sprugk2b.pdf ?

Jakez

Dear Jakez,

Thank you again!!!!

the MARn registers need to be set to 0 for the FPGA region(s) at system init (before cache init/reset), disabling cache in non-memory CEn domains (MARn are 0 at reset, see cache in megamodule user's guide spru871k.pdf). The megamodule and the EMIFA are independant subsystems.

I don't quit understand. You mean I don't have to consider about this part because megamodule and EMIFA are independent. Is that right??

I have check the register through CCSv5 and the register is just as what I set. I have seen SPRUK2b already!!!

Another question is how do you control the DSP??? I mean I communicate DSP by write C code through CCSv5. And you??  write asm code??

Still thank you very much.

Eric

Hello,

EMIFA and megamodule are independant since they have no shared configuration bits/registers, but cacheability (the MARn in megamodule) has to be controlled for non-memory devices.

EMIFA configuration in synchronous mode is full defined by writing to the CEnCFG register of interest. Without CSL, you may simply use something like (short way for CE2CFG):

*(unsigned*)0x70000080 = 0x80000001 + (read_latency (1..3) << 2) + (write_latency (0..3) << 6)

.Jakez

Dear Jakez,

Could you be kindly give me a sample code about the "total setting" of using EMIFA?

Because I'm using CSL, and use the  sample code inside, so maybe I miss something I don't know.

Thank you!!!

Eric

Hello,

In fact the minimalist line given is the EMIFA CE2 total setting (assuming RD_BE_EN, CE_EXT, R_ENABLE are 0) :

    *(unsigned*)0x70000080 = 0x80000001 + (read_latency (1..3) << 2) + (write_latency (0..3) << 6)

You may add (to assure MAR160 is set to 0, disabling CE2 cacheability):  

    *(unsigned*)0x01848280 = 0

Jakez

dear Jakez,

Do you mean that you can directly set registers by  *(unsigned*)0x01848280 = 0 this way?

I will do what you told to make sure MAR160 is right.

Another question is do I have to set Extended( or External) Memory Controller (EMC)?

The DSP block diagram in SPRUGK2B p.8, it seems that I have to set EMC before I use EMIFA, is that right?

It seems that the sample code which belongs to CSL6457 didn't consider about this part.

Thank you so much, and do you know why the staff of TI still Ignored these problems?? ^^"

Eric

Hello,

MARn registers are usually initialized at startup, with cache. They can be modified at any time (as in the dirty example: *(unsigned*)0x01848280 = 0 for MAR160, the first 16 MBytes of EMIFA CE2). If disabling an already enabled MARn, the cache should be purged from any existing reference to it before (a priori not the case for you)..

The Extended Memory Controller (see spru871) is a bridge internal to the megamodule, and needs no configuration by itself. It manages accesses between CPU, IDMA, peripheral registers, ressources external to megamodule (like EMIFA).

Jakez

Hello Jakez

I am new and a little bit lost could u tell me please how can i set up the project in  Code Composer  if i want to sent datas over emif interface of davince dm6437  to a RAM implemented on fpga. Which header files i need to include and is there  example source code in c?