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Bug in CGT 4.4.1 assembler or in c5515 silicon?

Craig Leeds
Intellectual 330 points

I'm using a C5515 EVM, a v3.0 core.  My assembler code contains the following mnemonic instruction:

   MANT AC0, AC0
   ::NEXP AC0, T1
   || SFTL AC1, #-31, AC1

On the simulator, everything works as expected: AC0, AC1, and T1 are all modified.   On the C5515, T1 and AC1 are modified as expected, but AC0 does not get modified.  I suspect that the v3.0 core is unable to shift both AC0 and AC1 in the same cycle.  If this is true and expected behavior, then the assembler should be modified to catch this type of parallel instruction.  If this is true but unexpected behavior, then the silicon errata should be updated.

  • 0
    TI__Guru* 84285 points

    According to the C55x v3.x CPU Reference Guide (SWPU073 revision E), the v3.0 core has a new functional unit "D-Unit Bit Manipulation Unit (D-Unit BIT)" which handles MANT::NEXP, so that instruction no longer uses the shifter.  Therefore, the assembler is correct.

    I cannot verify whether this is a silicon erratum, because I do not have a C5515 to test this.  Do you have a short test case which demonstrates the problem?  Make sure AC0 and AC1 are initialized.  Also make sure the parallel instruction is preceded and followed with 10 NOP instructions, just to make sure that the surrounding instructions aren't involved.

  • 0
    Intellectual 330 points

    I have created a C callable function.  

           void mantBug(void)

    It shows the bug when the instructions are paralleled, and also performs it correctly when it isn't paralleled.

    I was wrong about AC1 in the example.  My input value happened to be 0, so it correctly left AC1 as 0.  However, when I set the AC1 to 0xffdead0000, it didn't modify AC1 to 0x00000001 as it should have.  It left it at 0xffdead0000.  So the paralleled instruction does not perform the MANT nor the SFTL.

    By the way, I'm using CGT 4.4.1 with CCS 3.3.83.20.  And when I look at the disassembly code with CCS, it correctly disassembles it.

    Thanks for looking at it so quickly.

     I think that I uploaded the file.  I have inserted the contents of the file below in the event that it wasn't uploaded properly.

     

    *
    * The v3.0 core does not properly execute this parallel instruction.
    * This will modify T1 correctly, but not modify AC0 nor AC1.

    * The simulator works correctly. The bug has been reported.
    *

    .mmregs
    .def _mantBug
    .text
    _mantBug:
    *
    * Set initial Values of T1, AC0, AC1
    *
    MOV #0, T1 ; T1 = 0
    MOV #0x2800 << #16, AC0 ; AC0 = 0x0028000000
    MOV #0xdead << #16, AC1 ; AC1 = 0xffdead0000
    *
    * Clone T1, AC0, AC1 into T2, AC2, AC3 (so you can see what the code should do)
    *
    MOV T1, T2 ; T2 = 0
    MOV AC0, AC2 ; AC2 = 0x0028000000
    MOV AC1, AC3 ; AC3 = 0xffdead0000

    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    *
    * This paralleled instruction fails to modify AC0 and AC1
    *
    MANT AC0, AC0
    ::NEXP AC0, T1
    || SFTL AC1, #-31, AC1
    *
    * Expected value of AC0: 0x0050000000
    * Expected value of AC1: 0x0000000001
    * Expected value of T1: -1
    * Actual value of AC0: 0x0028000000
    * Actual value of AC1: 0xffdead0000
    * Actual value of T1: -1
    *
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    *
    * These non-paralleled instructions correcly modify AC0 and AC1
    *
    MANT AC2, AC2
    ::NEXP AC2, T2
    SFTL AC3, #-31, AC3
    *
    * Expected value of AC2: 0x0050000000
    * Expected value of AC3: 0x0000000001
    * Expected value of T2: -1
    * Actual value of AC2: 0x0050000000
    * Actual value of AC3: 0x0000000001
    * Actual value of T2: -1
    *
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    RET

    mantBug.asm